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-rw-r--r--src/cpu/x86/Kconfig2
-rw-r--r--src/cpu/x86/tsc/delay_tsc.c4
-rw-r--r--src/southbridge/amd/cs5536/Kconfig9
3 files changed, 4 insertions, 11 deletions
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index 325991e28e..3658ee7edc 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -19,7 +19,7 @@ config UDELAY_TSC
bool
default n
-config TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+config TSC_CALIBRATE_WITH_IO
bool
default n
diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c
index 1127867638..a77a61c774 100644
--- a/src/cpu/x86/tsc/delay_tsc.c
+++ b/src/cpu/x86/tsc/delay_tsc.c
@@ -7,7 +7,7 @@
static unsigned long clocks_per_usec;
-#if (CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 == 1)
+#if !CONFIG_TSC_CALIBRATE_WITH_IO
#define CLOCK_TICK_RATE 1193180U /* Underlying HZ */
/* ------ Calibrate the TSC -------
@@ -82,7 +82,7 @@ bad_ctc:
return 0;
}
-#else /* CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 */
+#else /* CONFIG_TSC_CALIBRATE_WITH_IO */
/*
* this is the "no timer2" version.
diff --git a/src/southbridge/amd/cs5536/Kconfig b/src/southbridge/amd/cs5536/Kconfig
index e7caf5e27a..18e3a2c853 100644
--- a/src/southbridge/amd/cs5536/Kconfig
+++ b/src/southbridge/amd/cs5536/Kconfig
@@ -19,12 +19,5 @@
config SOUTHBRIDGE_AMD_CS5536
bool
- select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-
-config UDELAY_TSC
- bool
- default y
- depends on SOUTHBRIDGE_AMD_CS5536
-
-
+ select UDELAY_TSC