diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/cannonlake/chip.h | 5 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/sata.h | 32 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/romstage/fsp_params.c | 22 |
3 files changed, 59 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 07a67cd630..0712146544 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -29,6 +29,7 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/pmc.h> +#include <soc/sata.h> #include <soc/serialio.h> #include <soc/usb.h> #include <soc/vr_config.h> @@ -39,6 +40,7 @@ #endif #define SOC_INTEL_CML_UART_DEV_MAX 3 +#define SOC_INTEL_CML_SATA_DEV_MAX 8 struct soc_intel_cannonlake_config { @@ -390,6 +392,9 @@ struct soc_intel_cannonlake_config { /* SATA Power Optimizer */ uint8_t satapwroptimize; + /* SATA Gen3 Strength */ + struct sata_port_config sata_port[SOC_INTEL_CML_SATA_DEV_MAX]; + /* Enable or disable eDP device */ uint8_t DdiPortEdp; diff --git a/src/soc/intel/cannonlake/include/soc/sata.h b/src/soc/intel/cannonlake/include/soc/sata.h new file mode 100644 index 0000000000..17802c3412 --- /dev/null +++ b/src/soc/intel/cannonlake/include/soc/sata.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef _SOC_SATA_H_ +#define _SOC_SATA_H_ + +#include <stdint.h> + +/* SATA Gen3 strength */ +struct sata_port_config { + uint8_t RxGen3EqBoostMagEnable; + uint8_t RxGen3EqBoostMag; + uint8_t TxGen3DownscaleAmpEnable; + uint8_t TxGen3DownscaleAmp; + uint8_t TxGen3DeEmphEnable; + uint8_t TxGen3DeEmph; +}; + +#endif diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 5c74d4a1e0..3c5be301b8 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -101,6 +101,28 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) dev = pcidev_path_on_root(SA_DEVFN_IPU); if (dev) m_cfg->SaIpuEnable = dev->enabled; + + /* SATA Gen3 strength */ + for (i = 0; i < SOC_INTEL_CML_SATA_DEV_MAX; i++) { + if (config->sata_port[i].RxGen3EqBoostMagEnable) { + m_cfg->PchSataHsioRxGen3EqBoostMagEnable[i] = + config->sata_port[i].RxGen3EqBoostMagEnable; + m_cfg->PchSataHsioRxGen3EqBoostMag[i] = + config->sata_port[i].RxGen3EqBoostMag; + } + if (config->sata_port[i].TxGen3DownscaleAmpEnable) { + m_cfg->PchSataHsioTxGen3DownscaleAmpEnable[i] = + config->sata_port[i].TxGen3DownscaleAmpEnable; + m_cfg->PchSataHsioTxGen3DownscaleAmp[i] = + config->sata_port[i].TxGen3DownscaleAmp; + } + if (config->sata_port[i].TxGen3DeEmphEnable) { + m_cfg->PchSataHsioTxGen3DeEmphEnable[i] = + config->sata_port[i].TxGen3DeEmphEnable; + m_cfg->PchSataHsioTxGen3DeEmph[i] = + config->sata_port[i].TxGen3DeEmph; + } + } } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) |