diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/southbridge/via/vt8237r/vt8237r.h | 1 | ||||
| -rw-r--r-- | src/southbridge/via/vt8237r/vt8237r_early_smbus.c | 9 |
2 files changed, 10 insertions, 0 deletions
diff --git a/src/southbridge/via/vt8237r/vt8237r.h b/src/southbridge/via/vt8237r/vt8237r.h index 54a46f8a72..d54c533aee 100644 --- a/src/southbridge/via/vt8237r/vt8237r.h +++ b/src/southbridge/via/vt8237r/vt8237r.h @@ -47,6 +47,7 @@ #define IDE_UDMA 0x50 /* SMBus */ +#define VT8237R_PSON 0x82 #define VT8237R_POWER_WELL 0x94 #define VT8237R_SMBUS_IO_BASE_REG 0xd0 #define VT8237R_SMBUS_HOST_CONF 0xd2 diff --git a/src/southbridge/via/vt8237r/vt8237r_early_smbus.c b/src/southbridge/via/vt8237r/vt8237r_early_smbus.c index 357ad819c0..4372a4a89d 100644 --- a/src/southbridge/via/vt8237r/vt8237r_early_smbus.c +++ b/src/southbridge/via/vt8237r/vt8237r_early_smbus.c @@ -132,12 +132,15 @@ u8 smbus_read_byte(u8 dimm, u8 offset) return val; } +#define PSONREADY_TIMEOUT 0x7fffffff + /** * Enable the SMBus on VT8237R-based systems. */ void enable_smbus(void) { device_t dev; + int loops; /* Power management controller */ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, @@ -150,6 +153,12 @@ void enable_smbus(void) die("Power management controller not found\n"); } + /* Make sure the RTC power well is up before touching smbus. */ + loops = 0; + while (!(pci_read_config8(dev, VT8237R_PSON) & (1<<6)) + && loops < PSONREADY_TIMEOUT) + ++loops; + /* * 7 = SMBus Clock from RTC 32.768KHz * 5 = Internal PLL reset from susp |