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-rw-r--r--src/southbridge/amd/pi/hudson/Kconfig8
-rw-r--r--src/southbridge/amd/pi/hudson/Makefile.inc13
2 files changed, 21 insertions, 0 deletions
diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig
index f6e3355ddb..7b3b7850a8 100644
--- a/src/southbridge/amd/pi/hudson/Kconfig
+++ b/src/southbridge/amd/pi/hudson/Kconfig
@@ -204,6 +204,14 @@ config AZ_PIN
bit 3,2 - pin 1
bit 5,4 - pin 2
bit 7,6 - pin 3
+
+config AMDFW_OUTSIDE_CBFS
+ def_bool n
+ help
+ The AMDFW (PSP) is typically locatable in cbfs. Select this
+ option to manually attach the generated amdfw.rom at an
+ offset of 0x20000 from the bottom of the coreboot ROM image.
+
endif
config HUDSON_UART
diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc
index 24a757ca3b..2153c62825 100644
--- a/src/southbridge/amd/pi/hudson/Makefile.inc
+++ b/src/southbridge/amd/pi/hudson/Makefile.inc
@@ -264,7 +264,20 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \
--flashsize $(CONFIG_ROM_SIZE) \
--output $@
+ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y)
+PHONY+=add_amdfw
+INTERMEDIATE+=add_amdfw
+
+add_amdfw: $(obj)/coreboot.pre $(obj)/amdfw.rom
+ printf " DD Adding AMD Firmware\n"
+ dd if=$(obj)/amdfw.rom \
+ of=$(obj)/coreboot.pre conv=notrunc bs=1 seek=131072 >/dev/null 2>&1
+
+else # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y)
+
cbfs-files-y += apu/amdfw
apu/amdfw-file := $(obj)/amdfw.rom
apu/amdfw-position := $(HUDSON_FWM_POSITION)
apu/amdfw-type := raw
+
+endif # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y)