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-rw-r--r--src/mainboard/google/sarien/ramstage.c12
-rw-r--r--src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl9
-rw-r--r--src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl9
3 files changed, 12 insertions, 18 deletions
diff --git a/src/mainboard/google/sarien/ramstage.c b/src/mainboard/google/sarien/ramstage.c
index 1d220461cf..811afa1b16 100644
--- a/src/mainboard/google/sarien/ramstage.c
+++ b/src/mainboard/google/sarien/ramstage.c
@@ -14,6 +14,7 @@
*/
#include <arch/acpi.h>
+#include <boardid.h>
#include <drivers/vpd/vpd.h>
#include <smbios.h>
#include <soc/gpio.h>
@@ -60,6 +61,13 @@ void smbios_fill_dimm_locator(const struct dimm_info *dimm,
}
#endif
+static const struct pad_config gpio_unused[] = {
+/* SUSWARN# */ PAD_NC(GPP_A13, NONE),
+/* SUSACK# */ PAD_NC(GPP_A15, NONE),
+/* M2_SKT2_CFG0 */ PAD_NC(GPP_H12, NONE),
+/* M2_SKT2_CFG1 */ PAD_NC(GPP_H13, NONE),
+};
+
void mainboard_silicon_init_params(FSP_S_CONFIG *params)
{
const struct pad_config *gpio_table;
@@ -67,6 +75,10 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
gpio_table = variant_gpio_table(&num_gpios);
cnl_configure_pads(gpio_table, num_gpios);
+
+ /* Disable unused pads for devices with board ID > 2 */
+ if (board_id() > 2)
+ gpio_configure_pads(gpio_unused, ARRAY_SIZE(gpio_unused));
}
static void mainboard_enable(struct device *dev)
diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl
index 4b05ba8e90..41121d28fe 100644
--- a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl
+++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl
@@ -15,8 +15,6 @@
#define CAM_EN GPP_B11 /* Active low */
#define TS_PD GPP_E7
-#define SSD_EN GPP_H13
-#define SSD_RST GPP_H12
/* Method called from LPIT prior to enter s0ix state */
Method (MS0X, 1)
@@ -37,13 +35,6 @@ Method (MPTS, 1)
/* Clear touch screen pd pin to avoid leakage */
\_SB.PCI0.CTXS (TS_PD)
-
- /* Clear SSD EN adn RST pin to avoid leakage */
- If (Arg0 == 5) {
- \_SB.PCI0.CTXS (SSD_RST)
- Sleep(1)
- \_SB.PCI0.CTXS (SSD_EN)
- }
}
/* Method called from _WAK prior to wakeup */
diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl
index 4b05ba8e90..41121d28fe 100644
--- a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl
+++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl
@@ -15,8 +15,6 @@
#define CAM_EN GPP_B11 /* Active low */
#define TS_PD GPP_E7
-#define SSD_EN GPP_H13
-#define SSD_RST GPP_H12
/* Method called from LPIT prior to enter s0ix state */
Method (MS0X, 1)
@@ -37,13 +35,6 @@ Method (MPTS, 1)
/* Clear touch screen pd pin to avoid leakage */
\_SB.PCI0.CTXS (TS_PD)
-
- /* Clear SSD EN adn RST pin to avoid leakage */
- If (Arg0 == 5) {
- \_SB.PCI0.CTXS (SSD_RST)
- Sleep(1)
- \_SB.PCI0.CTXS (SSD_EN)
- }
}
/* Method called from _WAK prior to wakeup */