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-rw-r--r--src/mainboard/google/samus/acpi/mainboard.asl8
-rw-r--r--src/mainboard/google/samus/devicetree.cb13
-rw-r--r--src/mainboard/google/samus/dsdt.asl2
3 files changed, 16 insertions, 7 deletions
diff --git a/src/mainboard/google/samus/acpi/mainboard.asl b/src/mainboard/google/samus/acpi/mainboard.asl
index 918e56580b..2140898809 100644
--- a/src/mainboard/google/samus/acpi/mainboard.asl
+++ b/src/mainboard/google/samus/acpi/mainboard.asl
@@ -58,6 +58,14 @@ Scope (\_SB)
}
/*
+ * LPC Trusted Platform Module
+ */
+Scope (\_SB.PCI0.LPCB)
+{
+ #include <drivers/pc80/tpm/acpi/tpm.asl>
+}
+
+/*
* WLAN connected to Root Port 3, becomes Root Port 1 after coalesce
*/
Scope (\_SB.PCI0.RP01)
diff --git a/src/mainboard/google/samus/devicetree.cb b/src/mainboard/google/samus/devicetree.cb
index b3596a4fa7..d12762d60c 100644
--- a/src/mainboard/google/samus/devicetree.cb
+++ b/src/mainboard/google/samus/devicetree.cb
@@ -94,13 +94,16 @@ chip soc/intel/broadwell
device pci 1d.0 off end # USB2 EHCI
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on
- chip ec/google/chromeec
- # We only have one init function that
- # we need to call to initialize the
- # keyboard part of the EC.
- device pnp ff.1 on # dummy address
+ chip drivers/pc80/tpm
+ # Rising edge interrupt
+ register "irq_polarity" = "2"
+ device pnp 0c31.0 on
+ irq 0x70 = 10
end
end
+ chip ec/google/chromeec
+ device pnp 0c09.0 on end
+ end
end # LPC bridge
device pci 1f.2 on end # SATA Controller
device pci 1f.3 off end # SMBus
diff --git a/src/mainboard/google/samus/dsdt.asl b/src/mainboard/google/samus/dsdt.asl
index cfd20371b0..722e0c9c93 100644
--- a/src/mainboard/google/samus/dsdt.asl
+++ b/src/mainboard/google/samus/dsdt.asl
@@ -18,8 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#define ENABLE_TPM
-
DefinitionBlock(
"dsdt.aml",
"DSDT",