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-rw-r--r--src/soc/intel/common/block/acpi/acpi/northbridge.asl4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl
index 1f58dfe720..53b21881ae 100644
--- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl
+++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl
@@ -182,8 +182,10 @@ Method (_CRS, 0, Serialized)
/*
* Fix up PCI memory region
* Start with Top of Lower Usable DRAM
+ * Lower 20 bits of TOLUD register need to be masked since they contain lock and
+ * reserved bits.
*/
- PMIN = \_SB.PCI0.MCHC.TLUD
+ PMIN = \_SB.PCI0.MCHC.TLUD & (0xfff << 20)
PLEN = PMAX - PMIN + 1
/* Patch PM02 range based on Memory Size */