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-rw-r--r--src/mainboard/getac/p470/romstage.c3
-rw-r--r--src/mainboard/hp/dl145_g3/romstage.c2
-rw-r--r--src/mainboard/hp/dl165_g6_fam10/romstage.c2
-rw-r--r--src/mainboard/ibase/mb899/romstage.c3
-rw-r--r--src/mainboard/intel/d945gclf/romstage.c3
-rw-r--r--src/mainboard/kontron/986lcd-m/romstage.c4
-rw-r--r--src/mainboard/roda/rk886ex/romstage.c3
-rw-r--r--src/southbridge/intel/i82801gx/i82801gx_usb_debug.c20
8 files changed, 16 insertions, 24 deletions
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index 9f7c14af52..7c55d0c591 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -37,7 +37,6 @@
#include <cpu/x86/bist.h>
#if CONFIG_USBDEBUG
-#define DBGP_DEFAULT 0
#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c"
#include "pc80/usbdebug_serial.c"
#endif
@@ -319,7 +318,7 @@ void main(unsigned long bist)
uart_init();
#if CONFIG_USBDEBUG
- i82801gx_enable_usbdebug(DBGP_DEFAULT);
+ i82801gx_enable_usbdebug(1);
early_usbdebug_init();
#endif
console_init();
diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c
index fb0d5eb5d5..8f3e21ddbe 100644
--- a/src/mainboard/hp/dl145_g3/romstage.c
+++ b/src/mainboard/hp/dl145_g3/romstage.c
@@ -44,8 +44,6 @@
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
-#define DBGP_DEFAULT 7
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c
index 0e0347d8c8..74ded075e9 100644
--- a/src/mainboard/hp/dl165_g6_fam10/romstage.c
+++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c
@@ -39,8 +39,6 @@
#define SET_FIDVID 1
#define SET_FIDVID_CORE_RANGE 0
-#define DBGP_DEFAULT 7
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index 8d4ca81254..4c953d7ab1 100644
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -40,7 +40,6 @@
#include <cpu/x86/bist.h>
#if CONFIG_USBDEBUG
-#define DBGP_DEFAULT 1
#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c"
#include "pc80/usbdebug_serial.c"
#endif
@@ -275,7 +274,7 @@ void main(unsigned long bist)
uart_init();
#if CONFIG_USBDEBUG
- i82801gx_enable_usbdebug(DBGP_DEFAULT);
+ i82801gx_enable_usbdebug(1);
early_usbdebug_init();
#endif
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index 43681a2d14..0b5c9c9cdb 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -39,7 +39,6 @@
#include <cpu/x86/bist.h>
#if CONFIG_USBDEBUG
-#define DBGP_DEFAULT 1
#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c"
#include "pc80/usbdebug_serial.c"
#endif
@@ -236,7 +235,7 @@ void main(unsigned long bist)
uart_init();
#if CONFIG_USBDEBUG
- i82801gx_enable_usbdebug(DBGP_DEFAULT);
+ i82801gx_enable_usbdebug(1);
early_usbdebug_init();
#endif
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index b3acece1f5..e400feea47 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -49,8 +49,6 @@
#include <cpu/x86/bist.h>
#if CONFIG_USBDEBUG
-#define DBGP_DEFAULT 1
-#include <usbdebug.h>
#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c"
#include "pc80/usbdebug_serial.c"
#endif
@@ -379,7 +377,7 @@ void main(unsigned long bist)
uart_init();
#if CONFIG_USBDEBUG
- i82801gx_enable_usbdebug(DBGP_DEFAULT);
+ i82801gx_enable_usbdebug(1);
early_usbdebug_init();
#endif
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index 00c4c9f446..a3e96651aa 100644
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -41,7 +41,6 @@
#include <cpu/x86/bist.h>
#if CONFIG_USBDEBUG
-#define DBGP_DEFAULT 1
#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c"
#include "pc80/usbdebug_serial.c"
#endif
@@ -291,7 +290,7 @@ void main(unsigned long bist)
uart_init();
#if CONFIG_USBDEBUG
- i82801gx_enable_usbdebug(DBGP_DEFAULT);
+ i82801gx_enable_usbdebug(1);
early_usbdebug_init();
#endif
diff --git a/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c b/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c
index 3539ef81e5..4fa3cb7aed 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c
@@ -17,6 +17,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <usbdebug.h>
+
// An arbitrary address for the BAR
#define EHCI_BAR 0xFEF00000
// These could be read from DEBUG_BASE (0:1d.7 R 0x5A 16bit)
@@ -26,22 +28,22 @@
#define EHCI_PORTSC 0x44
#define EHCI_DEBUG_OFFSET 0xA0
-#include <usbdebug.h>
+/* Required for successful build, but currently empty. */
+void set_debug_port(unsigned int port)
+{
+ /* Not needed, the ICH* southbridges hardcode physical USB port 1. */
+}
-void set_debug_port(unsigned port)
+static void i82801gx_enable_usbdebug(unsigned int port)
{
u32 dbgctl;
+ pci_write_config32(PCI_DEV(0, 0x1d, 7), EHCI_BAR_INDEX, EHCI_BAR);
+ pci_write_config8(PCI_DEV(0, 0x1d, 7), 0x04, 0x2); // Memory Space Enable
+
printk(BIOS_DEBUG, "Enabling OWNER_CNT\n");
dbgctl = read32(EHCI_BAR + EHCI_DEBUG_OFFSET);
dbgctl |= (1 << 30);
write32(EHCI_BAR + EHCI_DEBUG_OFFSET, dbgctl);
}
-static void i82801gx_enable_usbdebug(unsigned port)
-{
- pci_write_config32(PCI_DEV(0, 0x1d, 7), EHCI_BAR_INDEX, EHCI_BAR);
- pci_write_config8(PCI_DEV(0, 0x1d, 7), 0x04, 0x2); // Memory Space Enable
- set_debug_port(port);
-}
-