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-rw-r--r--src/mainboard/lippert/frontrunner-af/romstage.c12
-rw-r--r--src/mainboard/lippert/toucan-af/romstage.c12
-rw-r--r--src/northbridge/amd/agesa/family14/state_machine.c24
3 files changed, 24 insertions, 24 deletions
diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c
index 8a54555841..195ce4665a 100644
--- a/src/mainboard/lippert/frontrunner-af/romstage.c
+++ b/src/mainboard/lippert/frontrunner-af/romstage.c
@@ -23,15 +23,3 @@ void board_BeforeAgesa(struct sysinfo *cb)
{
smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
}
-
-#if 0
- post_code(0x40);
- /* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all
- * hang, looks like DRAM re-init goes wrong, don't know why. */
- val = agesawrapper_amdinitpost();
- if (val == 7) /* fatal, amdinitenv below is going to hang */
- outb(0x06, 0x0cf9); /* reset system harder instead */
-
- post_code(0x42);
- agesawrapper_amdinitenv();
-#endif
diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c
index 5128db0fa2..a3aea8d2d5 100644
--- a/src/mainboard/lippert/toucan-af/romstage.c
+++ b/src/mainboard/lippert/toucan-af/romstage.c
@@ -24,15 +24,3 @@ void board_BeforeAgesa(struct sysinfo *cb)
{
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
}
-
-#if 0
- post_code(0x40);
- /* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all
- * hang, looks like DRAM re-init goes wrong, don't know why. */
- val = agesawrapper_amdinitpost();
- if (val == 7) /* fatal, amdinitenv below is going to hang */
- outb(0x06, 0x0cf9); /* reset system harder instead */
-
- post_code(0x42);
- agesawrapper_amdinitenv();
-#endif
diff --git a/src/northbridge/amd/agesa/family14/state_machine.c b/src/northbridge/amd/agesa/family14/state_machine.c
index 81d15bc445..025d94fffd 100644
--- a/src/northbridge/amd/agesa/family14/state_machine.c
+++ b/src/northbridge/amd/agesa/family14/state_machine.c
@@ -16,7 +16,13 @@
#include "Porting.h"
#include "AGESA.h"
+#include <arch/io.h>
#include <cbmem.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <halt.h>
+#include <reset.h>
+#include <smp/node.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h>
@@ -24,6 +30,24 @@
void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
{
+ /* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all
+ * would fail later in AmdInitPost(), when DRAM is already configured
+ * and C6DramLock bit has been set.
+ *
+ * As a workaround, do a hard reset to clear C6DramLock bit.
+ */
+#ifdef __SIMPLE_DEVICE__
+ pci_devfn_t dev = PCI_DEV(0, 0x18, 2);
+#else
+ struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+#endif
+ if (boot_cpu()) {
+ u32 mct_cfg_lo = pci_read_config32(dev, 0x118);
+ if (mct_cfg_lo & (1<<19)) {
+ printk(BIOS_CRIT, "C6DramLock is set, resetting\n");
+ hard_reset();
+ }
+ }
}
void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early)