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-rw-r--r--src/mainboard/google/rambi/gpio.c34
-rw-r--r--src/soc/intel/baytrail/baytrail/gpio.h38
-rw-r--r--src/soc/intel/baytrail/gpio.c72
3 files changed, 102 insertions, 42 deletions
diff --git a/src/mainboard/google/rambi/gpio.c b/src/mainboard/google/rambi/gpio.c
index 8393e33855..3f913667db 100644
--- a/src/mainboard/google/rambi/gpio.c
+++ b/src/mainboard/google/rambi/gpio.c
@@ -20,6 +20,38 @@
#include <stdlib.h>
#include <baytrail/gpio.h>
+/* NCORE GPIOs */
+static const struct soc_gpio_map gpncore_gpio_map[] = {
+ GPIO_DEFAULT, /* GPIO 0 */
+ GPIO_DEFAULT, /* GPIO 1 */
+ GPIO_DEFAULT, /* GPIO 2 */
+ GPIO_DEFAULT, /* GPIO 3 */
+ GPIO_DEFAULT, /* GPIO 4 */
+ GPIO_DEFAULT, /* GPIO 5 */
+ GPIO_DEFAULT, /* GPIO 6 */
+ GPIO_DEFAULT, /* GPIO 7 */
+ GPIO_DEFAULT, /* GPIO 8 */
+ GPIO_DEFAULT, /* GPIO 9 */
+ GPIO_DEFAULT, /* GPIO 10 */
+ GPIO_DEFAULT, /* GPIO 11 */
+ GPIO_DEFAULT, /* GPIO 12 */
+ GPIO_DEFAULT, /* GPIO 13 */
+ GPIO_DEFAULT, /* GPIO 14 */
+ GPIO_DEFAULT, /* GPIO 15 */
+ GPIO_DEFAULT, /* GPIO 16 */
+ GPIO_DEFAULT, /* GPIO 17 */
+ GPIO_DEFAULT, /* GPIO 18 */
+ GPIO_DEFAULT, /* GPIO 19 */
+ GPIO_DEFAULT, /* GPIO 20 */
+ GPIO_DEFAULT, /* GPIO 21 */
+ GPIO_DEFAULT, /* GPIO 22 */
+ GPIO_DEFAULT, /* GPIO 23 */
+ GPIO_DEFAULT, /* GPIO 24 */
+ GPIO_DEFAULT, /* GPIO 25 */
+ GPIO_DEFAULT, /* GPIO 26 */
+ GPIO_END
+};
+
/* SCORE GPIOs */
static const struct soc_gpio_map gpscore_gpio_map[] = {
GPIO_DEFAULT, /* GPIO 0 */
@@ -177,7 +209,7 @@ static const struct soc_gpio_map gpssus_gpio_map[] = {
};
static struct soc_gpio_config gpio_config = {
- .ncore = NULL,
+ .ncore = gpncore_gpio_map,
.score = gpscore_gpio_map,
.ssus = gpssus_gpio_map
};
diff --git a/src/soc/intel/baytrail/baytrail/gpio.h b/src/soc/intel/baytrail/baytrail/gpio.h
index bdd36c104c..f62f5c80ad 100644
--- a/src/soc/intel/baytrail/baytrail/gpio.h
+++ b/src/soc/intel/baytrail/baytrail/gpio.h
@@ -142,25 +142,47 @@
* if not set correctly, even if the pin isn't configured as GPIO. */
#define PAD_VAL_DEFAULT (PAD_VAL_INPUT_ENABLE | PAD_VAL_OUTPUT_DISABLE)
+/* Configure GPIOs as legacy by default. GPNCORE doesn't support
+ * legacy config -- so also configure the pad regs as GPIO. We rely upon
+ * the fact that all GPNCORE pads are function 0 GPIO. */
#define GPIO_INPUT_PU_10K \
- { .pad_conf0 = PAD_PU_10K | PAD_PU_UP | PAD_CONFIG0_DEFAULT, \
+ { .pad_conf0 = PAD_PU_10K | PAD_PU_UP | PAD_CONFIG0_DEFAULT \
+ | PAD_FUNC0, \
+ .pad_conf1 = PAD_CONFIG1_DEFAULT, \
+ .pad_val = PAD_VAL_INPUT_ENABLE, \
+ .use_sel = GPIO_USE_LEGACY, \
+ .io_sel = GPIO_DIR_INPUT }
+
+#define GPIO_INPUT_PD_10K \
+ { .pad_conf0 = PAD_PU_10K | PAD_PU_DOWN | PAD_CONFIG0_DEFAULT \
+ | PAD_FUNC0, \
+ .pad_conf1 = PAD_CONFIG1_DEFAULT, \
+ .pad_val = PAD_VAL_INPUT_ENABLE, \
+ .use_sel = GPIO_USE_LEGACY, \
+ .io_sel = GPIO_DIR_INPUT }
+
+#define GPIO_INPUT_NOPU \
+ { .pad_conf0 = PAD_PU_10K | PAD_PU_DISABLE | PAD_CONFIG0_DEFAULT \
+ | PAD_FUNC0, \
.pad_conf1 = PAD_CONFIG1_DEFAULT, \
.pad_val = PAD_VAL_INPUT_ENABLE, \
.use_sel = GPIO_USE_LEGACY, \
.io_sel = GPIO_DIR_INPUT }
#define GPIO_OUT_LOW \
- { .pad_conf0 = PAD_PU_DISABLE | PAD_CONFIG0_DEFAULT, \
+ { .pad_conf0 = PAD_PU_DISABLE | PAD_CONFIG0_DEFAULT \
+ | PAD_FUNC0, \
.pad_conf1 = PAD_CONFIG1_DEFAULT, \
- .pad_val = PAD_VAL_OUTPUT_ENABLE, \
+ .pad_val = PAD_VAL_OUTPUT_ENABLE | PAD_VAL_LOW, \
.use_sel = GPIO_USE_LEGACY, \
.io_sel = GPIO_DIR_OUTPUT, \
.gp_lvl = GPIO_LEVEL_LOW }
#define GPIO_OUT_HIGH \
- { .pad_conf0 = PAD_PU_DISABLE | PAD_CONFIG0_DEFAULT, \
+ { .pad_conf0 = PAD_PU_DISABLE | PAD_CONFIG0_DEFAULT \
+ | PAD_FUNC0, \
.pad_conf1 = PAD_CONFIG1_DEFAULT, \
- .pad_val = PAD_VAL_OUTPUT_ENABLE, \
+ .pad_val = PAD_VAL_OUTPUT_ENABLE | PAD_VAL_HIGH, \
.use_sel = GPIO_USE_LEGACY, \
.io_sel = GPIO_DIR_OUTPUT, \
.gp_lvl = GPIO_LEVEL_HIGH }
@@ -214,8 +236,10 @@
{ .pad_conf0 = GPIO_LIST_END }
/* Common default GPIO settings */
-#define GPIO_INPUT GPIO_INPUT_PU_10K
-#define GPIO_UNUSED GPIO_INPUT_PU_10K
+#define GPIO_INPUT GPIO_INPUT_NOPU
+#define GPIO_INPUT_PU GPIO_INPUT_PU_10K
+#define GPIO_INPUT_PD GPIO_INPUT_PD_10K
+#define GPIO_NC GPIO_INPUT_PU_10K
#define GPIO_DEFAULT GPIO_FUNC0
struct soc_gpio_map {
diff --git a/src/soc/intel/baytrail/gpio.c b/src/soc/intel/baytrail/gpio.c
index 9ae79c9d4d..2916c999b6 100644
--- a/src/soc/intel/baytrail/gpio.c
+++ b/src/soc/intel/baytrail/gpio.c
@@ -23,53 +23,57 @@
/* GPIO-to-Pad LUTs */
static const u8 gpncore_gpio_to_pad[GPNCORE_COUNT] =
- { 25, 24, 23, 32, 33, 34, 36, 37, 35, 22,
- 20, 21, 18, 38, 39, 1, 4, 8, 17, 0,
- 3, 6, 16, 19, 2, 5, 9 };
+ { 25, 24, 23, 32, 33, 34, 36, 37, /* [ 0: 7] */
+ 35, 22, 20, 21, 18, 38, 39, 1, /* [ 8:15] */
+ 4, 8, 17, 0, 3, 6, 16, 19, /* [16:23] */
+ 2, 5, 9 }; /* [24:26] */
static const u8 gpscore_gpio_to_pad[GPSCORE_COUNT] =
- { 85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
- 36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
- 54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
- 52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
- 95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
- 86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
- 80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
- 2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
- 31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
- 24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
- 97, 100 };
+ { 85, 89, 93, 96, 99, 102, 98, 101, /* [ 0: 7] */
+ 34, 37, 36, 38, 39, 35, 40, 84, /* [ 8: 15] */
+ 62, 61, 64, 59, 54, 56, 60, 55, /* [16: 23] */
+ 63, 57, 51, 50, 53, 47, 52, 49, /* [24: 31] */
+ 48, 43, 46, 41, 45, 42, 58, 44, /* [32: 39] */
+ 95, 105, 70, 68, 67, 66, 69, 71, /* [40: 47] */
+ 65, 72, 86, 90, 88, 92, 103, 77, /* [48: 55] */
+ 79, 83, 78, 81, 80, 82, 13, 12, /* [56: 63] */
+ 15, 14, 17, 18, 19, 16, 2, 1, /* [64: 71] */
+ 0, 4, 6, 7, 9, 8, 33, 32, /* [72: 79] */
+ 31, 30, 29, 27, 25, 28, 26, 23, /* [80: 87] */
+ 21, 20, 24, 22, 5, 3, 10, 11, /* [88: 95] */
+ 106, 87, 91, 104, 97, 100 }; /* [96:101] */
static const u8 gpssus_gpio_to_pad[GPSSUS_COUNT] =
- { 29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
- 18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
- 0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
- 26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
- 52, 53, 59, 40 };
+ { 29, 33, 30, 31, 32, 34, 36, 35, /* [ 0: 7] */
+ 38, 37, 18, 7, 11, 20, 17, 1, /* [ 8:15] */
+ 8, 10, 19, 12, 0, 2, 23, 39, /* [16:23] */
+ 28, 27, 22, 21, 24, 25, 26, 51, /* [24:31] */
+ 56, 54, 49, 55, 48, 57, 50, 58, /* [32:39] */
+ 52, 53, 59, 40 }; /* [40:43] */
/* GPIO bank descriptions */
static const struct gpio_bank gpncore_bank = {
- .gpio_count = GPNCORE_COUNT,
- .gpio_to_pad = gpncore_gpio_to_pad,
- .legacy_base = GP_LEGACY_BASE_NONE,
- .pad_base = GPNCORE_PAD_BASE,
- .has_wake_en = 0,
+ .gpio_count = GPNCORE_COUNT,
+ .gpio_to_pad = gpncore_gpio_to_pad,
+ .legacy_base = GP_LEGACY_BASE_NONE,
+ .pad_base = GPNCORE_PAD_BASE,
+ .has_wake_en = 0,
};
static const struct gpio_bank gpscore_bank = {
- .gpio_count = GPSCORE_COUNT,
- .gpio_to_pad = gpscore_gpio_to_pad,
- .legacy_base = GPSCORE_LEGACY_BASE,
- .pad_base = GPSCORE_PAD_BASE,
- .has_wake_en = 0,
+ .gpio_count = GPSCORE_COUNT,
+ .gpio_to_pad = gpscore_gpio_to_pad,
+ .legacy_base = GPSCORE_LEGACY_BASE,
+ .pad_base = GPSCORE_PAD_BASE,
+ .has_wake_en = 0,
};
static const struct gpio_bank gpssus_bank = {
- .gpio_count = GPSSUS_COUNT,
- .gpio_to_pad = gpssus_gpio_to_pad,
- .legacy_base = GPSSUS_LEGACY_BASE,
- .pad_base = GPSSUS_PAD_BASE,
- .has_wake_en = 1,
+ .gpio_count = GPSSUS_COUNT,
+ .gpio_to_pad = gpssus_gpio_to_pad,
+ .legacy_base = GPSSUS_LEGACY_BASE,
+ .pad_base = GPSSUS_PAD_BASE,
+ .has_wake_en = 1,
};
static void setup_gpios(const struct soc_gpio_map *gpios,
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-25 15:09:13 +0000