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-rw-r--r--src/soc/amd/common/block/include/amdblocks/smbus.h50
-rw-r--r--src/soc/amd/common/block/smbus/smbus.c2
-rw-r--r--src/soc/amd/picasso/include/soc/southbridge.h44
-rw-r--r--src/soc/amd/picasso/southbridge.c1
-rw-r--r--src/soc/amd/stoneyridge/include/soc/southbridge.h44
-rw-r--r--src/soc/amd/stoneyridge/southbridge.c1
6 files changed, 53 insertions, 89 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/smbus.h b/src/soc/amd/common/block/include/amdblocks/smbus.h
new file mode 100644
index 0000000000..b618b78c34
--- /dev/null
+++ b/src/soc/amd/common/block/include/amdblocks/smbus.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef AMD_BLOCK_SMBUS_H
+#define AMD_BLOCK_SMBUS_H
+
+/* SMBUS MMIO offsets 0xfed80a00 */
+#define SMBHSTSTAT 0x0
+#define SMBHST_STAT_FAILED (1 << 4)
+#define SMBHST_STAT_COLLISION (1 << 3)
+#define SMBHST_STAT_ERROR (1 << 2)
+#define SMBHST_STAT_INTERRUPT (1 << 1)
+#define SMBHST_STAT_BUSY (1 << 0)
+#define SMBHST_STAT_CLEAR 0xff
+#define SMBHST_STAT_NOERROR (1 << 1) /* TODO: this one looks odd */
+#define SMBHST_STAT_VAL_BITS 0x1f
+#define SMBHST_STAT_ERROR_BITS 0x1c
+
+#define SMBSLVSTAT 0x1
+#define SMBSLV_STAT_ALERT (1 << 5)
+#define SMBSLV_STAT_SHADOW2 (1 << 4)
+#define SMBSLV_STAT_SHADOW1 (1 << 3)
+#define SMBSLV_STAT_SLV_STS (1 << 2)
+#define SMBSLV_STAT_SLV_INIT (1 << 1)
+#define SMBSLV_STAT_SLV_BUSY (1 << 0)
+#define SMBSLV_STAT_CLEAR 0x1f
+
+#define SMBHSTCTRL 0x2
+#define SMBHST_CTRL_RST (1 << 7)
+#define SMBHST_CTRL_STRT (1 << 6)
+#define SMBHST_CTRL_QCK_RW (0x0 << 2)
+#define SMBHST_CTRL_BTE_RW (0x1 << 2)
+#define SMBHST_CTRL_BDT_RW (0x2 << 2)
+#define SMBHST_CTRL_WDT_RW (0x3 << 2)
+#define SMBHST_CTRL_BLK_RW (0x5 << 2)
+#define SMBHST_CTRL_MODE_BITS (0x7 << 2)
+#define SMBHST_CTRL_KILL (1 << 1)
+#define SMBHST_CTRL_IEN (1 << 0)
+
+#define SMBHSTCMD 0x3
+#define SMBHSTADDR 0x4
+#define SMBHSTDAT0 0x5
+#define SMBHSTDAT1 0x6
+#define SMBHSTBLKDAT 0x7
+#define SMBSLVCTRL 0x8
+#define SMBSLVCMD_SHADOW 0x9
+#define SMBSLVEVT 0xa
+#define SMBSLVDAT 0xc
+#define SMBTIMING 0xe
+
+#endif /* AMD_BLOCK_SMBUS_H */
diff --git a/src/soc/amd/common/block/smbus/smbus.c b/src/soc/amd/common/block/smbus/smbus.c
index e30448312d..e94adf5bc6 100644
--- a/src/soc/amd/common/block/smbus/smbus.c
+++ b/src/soc/amd/common/block/smbus/smbus.c
@@ -5,7 +5,7 @@
#include <device/smbus_host.h>
#include <amdblocks/acpimmio.h>
#include <amdblocks/acpimmio_map.h>
-#include <soc/southbridge.h>
+#include <amdblocks/smbus.h>
/*
* Between 1-10 seconds, We should never timeout normally
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h
index 809eb97486..6fdc5abce8 100644
--- a/src/soc/amd/picasso/include/soc/southbridge.h
+++ b/src/soc/amd/picasso/include/soc/southbridge.h
@@ -93,50 +93,6 @@
#define PM_USB_ENABLE 0xef
#define PM_USB_ALL_CONTROLLERS 0x7f
-/* SMBUS MMIO offsets 0xfed80a00 */
-#define SMBHSTSTAT 0x0
-#define SMBHST_STAT_FAILED BIT(4)
-#define SMBHST_STAT_COLLISION BIT(3)
-#define SMBHST_STAT_ERROR BIT(2)
-#define SMBHST_STAT_INTERRUPT BIT(1)
-#define SMBHST_STAT_BUSY BIT(0)
-#define SMBHST_STAT_CLEAR 0xff
-#define SMBHST_STAT_NOERROR BIT(1)
-#define SMBHST_STAT_VAL_BITS 0x1f
-#define SMBHST_STAT_ERROR_BITS 0x1c
-
-#define SMBSLVSTAT 0x1
-#define SMBSLV_STAT_ALERT 0x20
-#define SMBSLV_STAT_SHADOW2 0x10
-#define SMBSLV_STAT_SHADOW1 0x08
-#define SMBSLV_STAT_SLV_STS 0x04
-#define SMBSLV_STAT_SLV_INIT 0x02
-#define SMBSLV_STAT_SLV_BUSY 0x01
-#define SMBSLV_STAT_CLEAR 0x1f
-
-#define SMBHSTCTRL 0x2
-#define SMBHST_CTRL_RST 0x80
-#define SMBHST_CTRL_STRT 0x40
-#define SMBHST_CTRL_QCK_RW 0x00
-#define SMBHST_CTRL_BTE_RW 0x04
-#define SMBHST_CTRL_BDT_RW 0x08
-#define SMBHST_CTRL_WDT_RW 0x0c
-#define SMBHST_CTRL_BLK_RW 0x14
-#define SMBHST_CTRL_MODE_BITS 0x1c
-#define SMBHST_CTRL_KILL 0x02
-#define SMBHST_CTRL_IEN 0x01
-
-#define SMBHSTCMD 0x3
-#define SMBHSTADDR 0x4
-#define SMBHSTDAT0 0x5
-#define SMBHSTDAT1 0x6
-#define SMBHSTBLKDAT 0x7
-#define SMBSLVCTRL 0x8
-#define SMBSLVCMD_SHADOW 0x9
-#define SMBSLVEVT 0xa
-#define SMBSLVDAT 0xc
-#define SMBTIMING 0xe
-
/* FCH MISC Registers 0xfed80e00 */
#define GPP_CLK_CNTRL 0x00
#define GPP_CLK0_REQ_SHIFT 0
diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c
index 9772e9bc31..edbcb60b5f 100644
--- a/src/soc/amd/picasso/southbridge.c
+++ b/src/soc/amd/picasso/southbridge.c
@@ -17,6 +17,7 @@
#include <amdblocks/espi.h>
#include <amdblocks/lpc.h>
#include <amdblocks/acpi.h>
+#include <amdblocks/smbus.h>
#include <amdblocks/spi.h>
#include <soc/acpi.h>
#include <soc/cpu.h>
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 59843c1ea8..d346197fb0 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -89,50 +89,6 @@
#define PM_USB_ENABLE 0xef
#define PM_USB_ALL_CONTROLLERS 0x7f
-/* SMBUS MMIO offsets 0xfed80a00 */
-#define SMBHSTSTAT 0x0
-#define SMBHST_STAT_FAILED 0x10
-#define SMBHST_STAT_COLLISION 0x08
-#define SMBHST_STAT_ERROR 0x04
-#define SMBHST_STAT_INTERRUPT 0x02
-#define SMBHST_STAT_BUSY 0x01
-#define SMBHST_STAT_CLEAR 0xff
-#define SMBHST_STAT_NOERROR 0x02
-#define SMBHST_STAT_VAL_BITS 0x1f
-#define SMBHST_STAT_ERROR_BITS 0x1c
-
-#define SMBSLVSTAT 0x1
-#define SMBSLV_STAT_ALERT 0x20
-#define SMBSLV_STAT_SHADOW2 0x10
-#define SMBSLV_STAT_SHADOW1 0x08
-#define SMBSLV_STAT_SLV_STS 0x04
-#define SMBSLV_STAT_SLV_INIT 0x02
-#define SMBSLV_STAT_SLV_BUSY 0x01
-#define SMBSLV_STAT_CLEAR 0x1f
-
-#define SMBHSTCTRL 0x2
-#define SMBHST_CTRL_RST 0x80
-#define SMBHST_CTRL_STRT 0x40
-#define SMBHST_CTRL_QCK_RW 0x00
-#define SMBHST_CTRL_BTE_RW 0x04
-#define SMBHST_CTRL_BDT_RW 0x08
-#define SMBHST_CTRL_WDT_RW 0x0c
-#define SMBHST_CTRL_BLK_RW 0x14
-#define SMBHST_CTRL_MODE_BITS 0x1c
-#define SMBHST_CTRL_KILL 0x02
-#define SMBHST_CTRL_IEN 0x01
-
-#define SMBHSTCMD 0x3
-#define SMBHSTADDR 0x4
-#define SMBHSTDAT0 0x5
-#define SMBHSTDAT1 0x6
-#define SMBHSTBLKDAT 0x7
-#define SMBSLVCTRL 0x8
-#define SMBSLVCMD_SHADOW 0x9
-#define SMBSLVEVT 0xa
-#define SMBSLVDAT 0xc
-#define SMBTIMING 0xe
-
/* FCH MISC Registers 0xfed80e00 */
#define GPP_CLK_CNTRL 0x00
#define GPP_CLK2_REQ_MAP_SHIFT 8
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index f411179c92..84872abc44 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -17,6 +17,7 @@
#include <amdblocks/acpimmio.h>
#include <amdblocks/lpc.h>
#include <amdblocks/acpi.h>
+#include <amdblocks/smbus.h>
#include <soc/southbridge.h>
#include <soc/smi.h>
#include <soc/amd_pci_int_defs.h>