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-rw-r--r--src/include/spd_cache.h2
-rw-r--r--src/lib/Kconfig17
-rw-r--r--src/lib/Makefile.inc2
-rw-r--r--src/mainboard/google/hatch/Kconfig1
4 files changed, 20 insertions, 2 deletions
diff --git a/src/include/spd_cache.h b/src/include/spd_cache.h
index 5465aadda4..a53b8eb948 100644
--- a/src/include/spd_cache.h
+++ b/src/include/spd_cache.h
@@ -7,7 +7,7 @@
#include <stddef.h>
#include <stdint.h>
-#define SPD_CACHE_FMAP_NAME "RW_SPD_CACHE"
+#define SPD_CACHE_FMAP_NAME (CONFIG_SPD_CACHE_FMAP_NAME)
#define SC_SPD_NUMS (CONFIG_DIMM_MAX)
#define SC_SPD_OFFSET(n) (CONFIG_DIMM_SPD_SIZE * n)
#define SC_CRC_OFFSET (CONFIG_DIMM_MAX * CONFIG_DIMM_SPD_SIZE)
diff --git a/src/lib/Kconfig b/src/lib/Kconfig
index 168a06801a..e1d56fe26b 100644
--- a/src/lib/Kconfig
+++ b/src/lib/Kconfig
@@ -46,6 +46,23 @@ config DIMM_SPD_SIZE
config SPD_READ_BY_WORD
bool
+config SPD_CACHE_IN_FMAP
+ bool
+ default n
+ help
+ Enables capability to cache DIMM SPDs in a dedicated FMAP region
+ to speed loading of SPD data. Currently requires board-level
+ romstage implementation to read/write/utilize cached SPD data.
+ When the default FMAP is used, will create a region named RW_SPD_CACHE
+ to store the cached SPD data.
+
+config SPD_CACHE_FMAP_NAME
+ string
+ depends on SPD_CACHE_IN_FMAP
+ default "RW_SPD_CACHE"
+ help
+ Name of the FMAP region created in the default FMAP to cache SPD data.
+
if RAMSTAGE_LIBHWBASE
config HWBASE_DYNAMIC_MMIO
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 07555a7b03..8424cbfac3 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -372,4 +372,4 @@ endif
ramstage-y += uuid.c
-romstage-$(CONFIG_ROMSTAGE_SPD_SMBUS) += spd_cache.c
+romstage-$(CONFIG_SPD_CACHE_IN_FMAP) += spd_cache.c
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig
index 20b71038d4..a4e91b6b0a 100644
--- a/src/mainboard/google/hatch/Kconfig
+++ b/src/mainboard/google/hatch/Kconfig
@@ -86,6 +86,7 @@ config ROMSTAGE_SPD_CBFS
config ROMSTAGE_SPD_SMBUS
bool
default n
+ select SPD_CACHE_IN_FMAP
config DRIVER_TPM_SPI_BUS
default 0x1