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-rw-r--r--src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb3
-rw-r--r--src/soc/intel/skylake/chip.c2
-rw-r--r--src/soc/intel/skylake/chip.h3
3 files changed, 1 insertions, 7 deletions
diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
index 782f3dc524..ad7c4abdba 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
@@ -105,9 +105,6 @@ chip soc/intel/skylake
.tdp_pl2_override = 60,
}"
- # Power Limit Related
- register "PowerLimit4" = "0"
-
# Lock Down
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 3eb72fa57a..c9519cdc29 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -303,7 +303,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi;
tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock;
- tconfig->PowerLimit4 = config->PowerLimit4;
+ tconfig->PowerLimit4 = 0;
/*
* To disable HECI, the Psf needs to be left unlocked
* by FSP till end of post sequence. Based on the devicetree
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 67739a4532..4d92410b65 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -87,9 +87,6 @@ struct soc_intel_skylake_config {
/* TCC activation offset */
uint32_t tcc_offset;
- /* Package PL4 power limit in Watts */
- u32 PowerLimit4;
-
/* Whether to ignore VT-d support of the SKU */
int ignore_vtd;