3 files changed, 40 insertions, 33 deletions
diff --git a/src/cpu/k8/Config.lb b/src/cpu/k8/Config.lb
index 7a83d3e846..f1f63e263e 100644
--- a/src/cpu/k8/Config.lb
+++ b/src/cpu/k8/Config.lb
@@ -1,4 +1,5 @@
 uses CPU_FIXUP
 if CPU_FIXUP
   object cpufixup.o
+  object apic_timer.o
 end
diff --git a/src/superio/NSC/pc87360/chip.h b/src/superio/NSC/pc87360/chip.h
index 39c58cf7bc..04bdea30de 100644
--- a/src/superio/NSC/pc87360/chip.h
+++ b/src/superio/NSC/pc87360/chip.h
@@ -1,5 +1,18 @@
+#ifndef PNP_INDEX_REG
+#define PNP_INDEX_REG   0x15C
+#endif
+#ifndef PNP_DATA_REG
+#define PNP_DATA_REG    0x15D
+#endif
+#ifndef SIO_COM1
+#define SIO_COM1_BASE   0x3F8
+#endif
+#ifndef SIO_COM2
+#define SIO_COM2_BASE   0x2F8
+#endif
 
 struct superio_NSC_pc87360_config {
-    typedef struct com_ports com1;
-    typedef struct lpt_ports lpt;
+    struct com_ports com1;
+    struct lpt_ports lpt;
+    int port;
 };
diff --git a/src/superio/NSC/pc87360/superio.c b/src/superio/NSC/pc87360/superio.c
index aa4b668000..9908fd8595 100644
--- a/src/superio/NSC/pc87360/superio.c
+++ b/src/superio/NSC/pc87360/superio.c
@@ -1,44 +1,37 @@
 /* Copyright 2000  AG Electronics Ltd. */
 /* This code is distributed without warranty under the GPL v2 (see COPYING) */
 
-#include <types.h>
 #include <arch/io.h>
+#include <device/chip.h>
+#include "chip.h"
 
-#ifndef PNP_INDEX_REG
-#define PNP_INDEX_REG	0x15C
-#endif
-#ifndef PNP_DATA_REG
-#define PNP_DATA_REG	0x15D
-#endif
-#ifndef SIO_COM1
-#define SIO_COM1_BASE	0x3F8
-#endif
-#ifndef SIO_COM2
-#define SIO_COM2_BASE	0x2F8
-#endif
-
-static
 void pnp_output(char address, char data)
 {
-    outb(address, PNP_INDEX_REG);
-    outb(data, PNP_DATA_REG);
+	outb(address, PNP_INDEX_REG);
+	outb(data, PNP_DATA_REG);
 }
 
-static
-void sio_enable(void)
+void sio_enable(struct chip *chip, enum chip_pass pass)
 {
-    /* Enable Super IO Chip */
-    pnp_output(0x07, 6); /* LD 6 = UART1 */
-    pnp_output(0x30, 0); /* Dectivate */
-    pnp_output(0x60, SIO_COM1_BASE >> 8); /* IO Base */
-    pnp_output(0x61, SIO_COM1_BASE & 0xFF); /* IO Base */
-    pnp_output(0x30, 1); /* Activate */
+
+	struct superio_NSC_pc87360_config *conf = (struct superio_NSC_pc87360_config *)chip->chip_info;
+
+	switch (pass) {
+	case CHIP_PRE_CONSOLE:
+		/* Enable Super IO Chip */
+		pnp_output(0x07, 6); /* LD 6 = UART1 */
+		pnp_output(0x30, 0); /* Dectivate */
+		pnp_output(0x60, conf->port >> 8); /* IO Base */
+		pnp_output(0x61, conf->port & 0xFF); /* IO Base */
+		pnp_output(0x30, 1); /* Activate */
+		break;
+	default:
+		/* nothing yet */
+		break;
+	}
 }
 
-struct superio_control superio_NSC_pc87360_control = {
-	pre_pci_init:   (void *)0,
-	init:           (void *)0,
-	finishup:       (void *)0,
-	defaultport:    SIO_COM1_BASE,
-	name:           "NSC pc87360"
+struct chip_control superio_NSC_pc87360_control = {
+	enable: sio_enable,
+	name:   "NSC 87360"
 };