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-rw-r--r--src/mainboard/google/octopus/variants/ampton/overridetree.cb41
1 files changed, 41 insertions, 0 deletions
diff --git a/src/mainboard/google/octopus/variants/ampton/overridetree.cb b/src/mainboard/google/octopus/variants/ampton/overridetree.cb
index 1b4b9ba6a9..10ff7d74f7 100644
--- a/src/mainboard/google/octopus/variants/ampton/overridetree.cb
+++ b/src/mainboard/google/octopus/variants/ampton/overridetree.cb
@@ -1,5 +1,46 @@
chip soc/intel/apollolake
+ # EMMC Tx CMD Delay
+ # Refer to EDS-Vol2-16.32.
+ # [14:8] steps of delay for DDR mode, each 125ps.
+ # [6:0] steps of delay for SDR mode, each 125ps.
+ register "emmc_tx_cmd_cntl" = "0x505"
+
+ # EMMC TX DATA Delay 1
+ # Refer to EDS-Vol2-16.33.
+ # [14:8] steps of delay for HS400, each 125ps.
+ # [6:0] steps of delay for SDR104/HS200, each 125ps.
+ register "emmc_tx_data_cntl1" = "0x0a0c"
+
+ # EMMC TX DATA Delay 2
+ # Refer to EDS-Vol2-16.34.
+ # [30:24] steps of delay for SDR50, each 125ps.
+ # [22:16] steps of delay for DDR50, each 125ps.
+ # [14:8] steps of delay for SDR25/HS50, each 125ps.
+ # [6:0] steps of delay for SDR12, each 125ps.
+ register "emmc_tx_data_cntl2" = "0x1c292929"
+
+ # EMMC RX CMD/DATA Delay 1
+ # Refer to EDS-Vol2-16.35.
+ # [30:24] steps of delay for SDR50, each 125ps.
+ # [22:16] steps of delay for DDR50, each 125ps.
+ # [14:8] steps of delay for SDR25/HS50, each 125ps.
+ # [6:0] steps of delay for SDR12, each 125ps.
+ register "emmc_rx_cmd_data_cntl1" = "0x001a1c1c"
+
+ # EMMC RX CMD/DATA Delay 2
+ # Refer to EDS-Vol2-16.37.
+ # [17:16] stands for Rx Clock before Output Buffer
+ # [14:8] steps of delay for Auto Tuning Mode, each 125ps.
+ # [6:0] steps of delay for HS200, each 125ps.
+ register "emmc_rx_cmd_data_cntl2" = "0x10026"
+
+ # EMMC Rx Strobe Delay
+ # Refer to EDS-Vol2-16.36.
+ # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps.
+ # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps.
+ register "emmc_rx_strobe_cntl" = "0x0a0a"
+
register "common_soc_config" = "{
.gspi[0] = {
.speed_mhz = 1,