diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/amd/dinar/Kconfig | 4 | ||||
| -rw-r--r-- | src/mainboard/amd/dinar/romstage.c | 5 | ||||
| -rw-r--r-- | src/mainboard/asrock/e350m1/Kconfig | 4 | ||||
| -rw-r--r-- | src/mainboard/asrock/e350m1/romstage.c | 2 | ||||
| -rw-r--r-- | src/mainboard/avalue/eax-785e/Kconfig | 4 | ||||
| -rw-r--r-- | src/mainboard/avalue/eax-785e/romstage.c | 3 | ||||
| -rw-r--r-- | src/mainboard/intel/cougar_canyon2/Kconfig | 4 | ||||
| -rw-r--r-- | src/mainboard/intel/cougar_canyon2/romstage.c | 6 | ||||
| -rw-r--r-- | src/mainboard/supermicro/h8qgi/Kconfig | 7 | ||||
| -rw-r--r-- | src/mainboard/supermicro/h8qgi/romstage.c | 6 | ||||
| -rw-r--r-- | src/mainboard/supermicro/h8scm/Kconfig | 7 | ||||
| -rw-r--r-- | src/mainboard/tyan/s8226/Kconfig | 7 |
12 files changed, 14 insertions, 45 deletions
diff --git a/src/mainboard/amd/dinar/Kconfig b/src/mainboard/amd/dinar/Kconfig index 30afa95233..e826459968 100644 --- a/src/mainboard/amd/dinar/Kconfig +++ b/src/mainboard/amd/dinar/Kconfig @@ -72,10 +72,6 @@ config RAMBASE hex default 0x200000 -config SIO_PORT - hex - default 0x2e - config DRIVERS_PS2_KEYBOARD bool default y diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index 8ed1398521..0b52ea9249 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -37,8 +37,7 @@ #include "Platform.h" #include <arch/cpu.h> -#define SERIAL_DEV PNP_DEV(CONFIG_SIO_PORT, SMSCSUPERIO_SP1) - +#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) u32 agesawrapper_amdinitmmio (void); u32 agesawrapper_amdinitreset (void); @@ -58,7 +57,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x30); - sch4037_early_init (CONFIG_SIO_PORT); + sch4037_early_init(0x2e); /* Detect SMSC SIO1036 LPC Debug Card status */ if (detect_sio1036_chip(0x4E)) { diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig index 956bb3ce5b..00cdaa735c 100644 --- a/src/mainboard/asrock/e350m1/Kconfig +++ b/src/mainboard/asrock/e350m1/Kconfig @@ -69,10 +69,6 @@ config RAMBASE hex default 0x200000 -config SIO_PORT - hex - default 0x2e - config ONBOARD_VGA_IS_PRIMARY bool default y diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index 2913c08da0..5c2f86747f 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -39,7 +39,7 @@ #include "SBPLATFORM.h" -#define SERIAL_DEV PNP_DEV(CONFIG_SIO_PORT, W83627HF_SP1) +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/avalue/eax-785e/Kconfig b/src/mainboard/avalue/eax-785e/Kconfig index 4c11a8a81d..32b2affa0c 100644 --- a/src/mainboard/avalue/eax-785e/Kconfig +++ b/src/mainboard/avalue/eax-785e/Kconfig @@ -89,8 +89,4 @@ config VGA_BIOS_ID string default "1002,9712" -config SIO_PORT - hex - default 0x2E - endif #BOARD_AVALUE_EAX_785E diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index f6a10dcb7b..883bd11cf7 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -52,6 +52,7 @@ #include "northbridge/amd/amdfam10/debug.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +#define CLK_DEV PNP_DEV(0x2e, W83627HF_SP1) static void activate_spd_rom(const struct mem_controller *ctrl) { @@ -102,7 +103,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_rs780_dev8(); sb800_clk_output_48Mhz(); - w83627hf_set_clksel_48(PNP_DEV(CONFIG_SIO_PORT, 0)); + w83627hf_set_clksel_48(CLK_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/intel/cougar_canyon2/Kconfig b/src/mainboard/intel/cougar_canyon2/Kconfig index ad3a404a14..389a13cd47 100644 --- a/src/mainboard/intel/cougar_canyon2/Kconfig +++ b/src/mainboard/intel/cougar_canyon2/Kconfig @@ -35,10 +35,6 @@ config MAX_CPUS int default 16 -config SIO_PORT - hex - default 0x164e - config SMBIOS_SYSTEM_ENCLOSURE_TYPE hex default 0x09 # This is a mobile platform diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c index 69389257d2..add6ddc192 100644 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ b/src/mainboard/intel/cougar_canyon2/romstage.c @@ -44,6 +44,8 @@ #include "gpio.h" #include <arch/stages.h> +#define SIO_PORT 0x164e + static inline void reset_system(void) { hard_reset(); @@ -69,7 +71,7 @@ static void pch_enable_lpc(void) /* Map a range for the runtime registers to the LPC bus. */ pci_write_config32(dev, LPC_GEN2_DEC, 0xc0181); - if (sio1007_enable_uart_at(CONFIG_SIO_PORT)) { + if (sio1007_enable_uart_at(SIO_PORT)) { pci_write_config16(dev, LPC_EN, lpc_config | COMA_LPC_EN); } @@ -77,7 +79,7 @@ static void pch_enable_lpc(void) static void setup_sio_gpios(void) { - const u16 port = CONFIG_SIO_PORT; + const u16 port = SIO_PORT; const u16 runtime_port = 0x180; /* Turn on configuration mode. */ diff --git a/src/mainboard/supermicro/h8qgi/Kconfig b/src/mainboard/supermicro/h8qgi/Kconfig index 44057ae497..ee78a2fbba 100644 --- a/src/mainboard/supermicro/h8qgi/Kconfig +++ b/src/mainboard/supermicro/h8qgi/Kconfig @@ -72,13 +72,6 @@ config RAMBASE hex default 0x200000 -config SIO_PORT - hex - default 0x164E - help - though UARTs are on the NUVOTON BMC, port 0x164E - PS2 keyboard and mouse are on SUPERIO_WINBOND_W83627DHG, port 0x2E - config DRIVERS_PS2_KEYBOARD bool default y diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c index f9d3ba1a6e..d95db3c6f6 100644 --- a/src/mainboard/supermicro/h8qgi/romstage.c +++ b/src/mainboard/supermicro/h8qgi/romstage.c @@ -35,6 +35,10 @@ #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> +/* though UARTs are on the NUVOTON BMC, port 0x164E + * PS2 keyboard and mouse are on SUPERIO_WINBOND_W83627DHG, port 0x2E + */ +#define SIO_PORT 0x164e void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -49,7 +53,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) report_bist_failure(bist); sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */ - wpcm450_enable_dev(WPCM450_SP1, CONFIG_SIO_PORT, CONFIG_TTYS0_BASE); + wpcm450_enable_dev(WPCM450_SP1, SIO_PORT, CONFIG_TTYS0_BASE); sb7xx_51xx_disable_wideio(0); post_code(0x34); diff --git a/src/mainboard/supermicro/h8scm/Kconfig b/src/mainboard/supermicro/h8scm/Kconfig index 2b4cec042c..a9757dfb62 100644 --- a/src/mainboard/supermicro/h8scm/Kconfig +++ b/src/mainboard/supermicro/h8scm/Kconfig @@ -75,13 +75,6 @@ config RAMBASE hex default 0x200000 -config SIO_PORT - hex - default 0x164E - help - though UARTs are on the NUVOTON BMC, port 0x164E - PS2 keyboard and mouse are on SUPERIO_WINBOND_W83627DHG, port 0x2E - config DRIVERS_PS2_KEYBOARD bool default y diff --git a/src/mainboard/tyan/s8226/Kconfig b/src/mainboard/tyan/s8226/Kconfig index d9163d46fa..64aa29a857 100644 --- a/src/mainboard/tyan/s8226/Kconfig +++ b/src/mainboard/tyan/s8226/Kconfig @@ -72,13 +72,6 @@ config RAMBASE hex default 0x200000 -config SIO_PORT - hex - default 0x164E - help - though UARTs are on the NUVOTON BMC, port 0x164E - PS2 keyboard and mouse are on SUPERIO_WINBOND_W83627DHG, port 0x2E - config DRIVERS_PS2_KEYBOARD bool default y |