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-rw-r--r--src/soc/intel/fsp_broadwell_de/include/soc/ubox.h3
-rw-r--r--src/soc/intel/fsp_broadwell_de/romstage/romstage.c36
-rw-r--r--src/soc/intel/fsp_broadwell_de/southcluster.c23
-rw-r--r--src/soc/intel/fsp_broadwell_de/ubox.c7
4 files changed, 45 insertions, 24 deletions
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/ubox.h b/src/soc/intel/fsp_broadwell_de/include/soc/ubox.h
index baaeac55cb..3c2e6f50a6 100644
--- a/src/soc/intel/fsp_broadwell_de/include/soc/ubox.h
+++ b/src/soc/intel/fsp_broadwell_de/include/soc/ubox.h
@@ -40,6 +40,5 @@
#define UBOX_DEVHIDE0 0xb0
-void iio_hide(const uint8_t devno, const uint8_t funcno);
-
+void iio_hide(DEVTREE_CONST struct device *dev);
#endif
diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
index b0fad3f02b..8438b1035c 100644
--- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
+++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
@@ -94,6 +94,37 @@ static void enable_integrated_uart(uint8_t port)
pci_mmio_write_config32(ubox_dev, UBOX_UART_ENABLE, ubox_uart_en);
}
+static void early_iio_hide(void)
+{
+ DEVTREE_CONST struct device *dev;
+
+ const pci_devfn_t iio_rootport[] = {
+ PCI_DEVFN(PCIE_IIO_PORT_1_DEV, PCIE_IIO_PORT_1A_FUNC),
+ PCI_DEVFN(PCIE_IIO_PORT_1_DEV, PCIE_IIO_PORT_1B_FUNC),
+ PCI_DEVFN(PCIE_IIO_PORT_2_DEV, PCIE_IIO_PORT_2A_FUNC),
+ PCI_DEVFN(PCIE_IIO_PORT_2_DEV, PCIE_IIO_PORT_2B_FUNC),
+ PCI_DEVFN(PCIE_IIO_PORT_2_DEV, PCIE_IIO_PORT_2C_FUNC),
+ PCI_DEVFN(PCIE_IIO_PORT_2_DEV, PCIE_IIO_PORT_2D_FUNC),
+ PCI_DEVFN(PCIE_IIO_PORT_3_DEV, PCIE_IIO_PORT_3A_FUNC),
+ PCI_DEVFN(PCIE_IIO_PORT_3_DEV, PCIE_IIO_PORT_3B_FUNC),
+ PCI_DEVFN(PCIE_IIO_PORT_3_DEV, PCIE_IIO_PORT_3C_FUNC),
+ PCI_DEVFN(PCIE_IIO_PORT_3_DEV, PCIE_IIO_PORT_3D_FUNC),
+ };
+
+ /* Walk through IIO root ports and hide if it is disabled in devtree */
+ for (int i = 0; i < ARRAY_SIZE(iio_rootport); i++) {
+ dev = pcidev_path_on_bus(BUS0, iio_rootport[i]);
+ if (dev && !dev->enabled) {
+ printk(BIOS_DEBUG, "Hiding IIO root port: %d:%d.%d\n",
+ BUS0,
+ PCI_SLOT(iio_rootport[i]),
+ PCI_FUNC(iio_rootport[i]));
+ iio_hide(dev);
+ }
+ }
+
+}
+
/* Entry from cache-as-ram.inc. */
void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header)
{
@@ -121,14 +152,15 @@ void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header)
init_rtc();
setup_gpio_io_address();
+ /* Hide before MemoryInit since hiding later seems to break FSP */
+ early_iio_hide();
timestamp_add_now(TS_BEFORE_INITRAM);
-
+ post_code(0x48);
/*
* Call early init to initialize memory and chipset. This function returns
* to the romstage_main_continue function with a pointer to the HOB
* structure.
*/
- post_code(0x48);
printk(BIOS_DEBUG, "Starting the Intel FSP (early_init)\n");
fsp_early_init(fsp_info_header);
die_with_post_code(POST_INVALID_VENDOR_BINARY,
diff --git a/src/soc/intel/fsp_broadwell_de/southcluster.c b/src/soc/intel/fsp_broadwell_de/southcluster.c
index d1981fd75b..fb8af87b62 100644
--- a/src/soc/intel/fsp_broadwell_de/southcluster.c
+++ b/src/soc/intel/fsp_broadwell_de/southcluster.c
@@ -257,24 +257,11 @@ void southcluster_enable_dev(struct device *dev)
const int slot = PCI_SLOT(dev->path.pci.devfn);
const int func = PCI_FUNC(dev->path.pci.devfn);
- switch (slot) {
- case PCIE_IIO_PORT_0_DEV:
- die("should not hide PCH link");
- case PCIE_IIO_PORT_1_DEV: /* fallthrough */
- case PCIE_IIO_PORT_2_DEV: /* fallthrough */
- case PCIE_IIO_PORT_3_DEV: /* fallthrough */
- printk(BIOS_DEBUG, "%s: Disabling IOU bridge %02x.%01x\n", dev_path(dev), slot,
- func);
- iio_hide(slot, func);
- break;
- default:
- printk(BIOS_DEBUG, "%s: Disabling device: %02x.%01x\n", dev_path(dev), slot,
- func);
- /* Ensure memory, io, and bus master are all disabled */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
- pci_write_config32(dev, PCI_COMMAND, reg32);
- }
+ printk(BIOS_DEBUG, "%s: Disabling device: %02x.%01x\n", dev_path(dev), slot, func);
+ /* Ensure memory, io, and bus master are all disabled */
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
+ pci_write_config32(dev, PCI_COMMAND, reg32);
}
#if CONFIG(HAVE_ACPI_TABLES)
diff --git a/src/soc/intel/fsp_broadwell_de/ubox.c b/src/soc/intel/fsp_broadwell_de/ubox.c
index d7352ad667..e3e55e0624 100644
--- a/src/soc/intel/fsp_broadwell_de/ubox.c
+++ b/src/soc/intel/fsp_broadwell_de/ubox.c
@@ -18,10 +18,13 @@
#include <stdint.h>
#include <soc/ubox.h>
-void iio_hide(const uint8_t devno, const uint8_t funcno)
+void iio_hide(DEVTREE_CONST struct device *dev)
{
pci_devfn_t ubox_dev;
+ uint8_t slot, func;
+ slot = PCI_SLOT(dev->path.pci.devfn);
+ func = PCI_FUNC(dev->path.pci.devfn);
ubox_dev = PCI_DEV(get_busno1(), UBOX_DEV, UBOX_FUNC);
- pci_or_config32(ubox_dev, UBOX_DEVHIDE0 + funcno * 4, 1 << devno);
+ pci_or_config32(ubox_dev, UBOX_DEVHIDE0 + func * 4, 1 << slot);
}