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-rw-r--r--src/mainboard/pcengines/apu2/romstage.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c
index a4bd816506..a1720d2ab4 100644
--- a/src/mainboard/pcengines/apu2/romstage.c
+++ b/src/mainboard/pcengines/apu2/romstage.c
@@ -105,6 +105,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39);
AGESAWRAPPER(amdinitearly);
+ /* Disable SVI2 controller to wait for command completion */
+ val = pci_read_config32(PCI_DEV(0, 0x18, 5), 0x12C);
+ if (val & (1 << 30)) {
+ printk(BIOS_DEBUG, "SVI2 Wait completion disabled\n");
+ } else {
+ printk(BIOS_DEBUG, "Disabling SVI2 Wait completion\n");
+ val |= (1 << 30);
+ pci_write_config32(PCI_DEV(0, 0x18, 5), 0x12C, val);
+ }
+
timestamp_add_now(TS_BEFORE_INITRAM);
post_code(0x40);