diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/hatch/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 6 |
2 files changed, 7 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index b6dec1381e..6b4e45f91b 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -6,6 +6,7 @@ config BOARD_GOOGLE_BASEBOARD_HATCH select DRIVERS_I2C_HID select DRIVERS_SPI_ACPI select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_LPC select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select MAINBOARD_HAS_CHROMEOS diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 2e171b0579..3cdc3e01a1 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -10,6 +10,12 @@ chip soc/intel/cannonlake register "gpe0_dw1" = "PMC_GPP_C" register "gpe0_dw2" = "PMC_GPP_D" + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | |