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-rw-r--r--src/arch/x86/Makefile.inc28
-rw-r--r--src/cpu/Kconfig88
-rw-r--r--src/cpu/Makefile.inc37
-rw-r--r--src/cpu/intel/microcode/Makefile.inc20
-rw-r--r--src/cpu/intel/microcode/microcode.c8
-rw-r--r--src/cpu/intel/model_206ax/Kconfig2
-rw-r--r--src/cpu/intel/model_206ax/Makefile.inc2
-rw-r--r--src/cpu/intel/model_206ax/microcode_blob.c (renamed from src/cpu/intel/microcode/microcode_blob.c)2
-rw-r--r--src/include/cpu/intel/microcode.h2
9 files changed, 147 insertions, 42 deletions
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 810e168895..c58f3be1b7 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -1,6 +1,8 @@
+################################################################################
##
## This file is part of the coreboot project.
##
+## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
## Copyright (C) 2009-2010 coresystems GmbH
## Copyright (C) 2009 Ronald G. Minnich
##
@@ -17,8 +19,8 @@
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
+################################################################################
-#######################################################################
# Take care of subdirectories
subdirs-y += boot
# subdirs-y += init
@@ -34,13 +36,7 @@ cmos_layout.bin-type = 0x01aa
OPTION_TABLE_H:=$(obj)/option_table.h
endif
-ifeq ($(CONFIG_MICROCODE_IN_CBFS),y)
-cbfs-files-y += microcode_blob.bin
-microcode_blob.bin-file = $(obj)/microcode_blob.bin
-microcode_blob.bin-type = 0x53
-endif
-
-#######################################################################
+################################################################################
# Build the final rom image
COREBOOT_ROM_DEPENDENCIES:=
ifeq ($(CONFIG_PAYLOAD_ELF),y)
@@ -125,7 +121,7 @@ cbfs-files-$(CONFIG_BOOTSPLASH) += bootsplash.jpg
bootsplash.jpg-file := $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE))
bootsplash.jpg-type := bootsplash
-#######################################################################
+################################################################################
# i386 specific tools
NVRAMTOOL:=$(objutil)/nvramtool/nvramtool
@@ -137,7 +133,7 @@ $(obj)/cmos_layout.bin: $(NVRAMTOOL) $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.l
@printf " OPTION $(subst $(obj)/,,$(@))\n"
$(NVRAMTOOL) -y $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout -L $@
-#######################################################################
+################################################################################
# Common recipes for all stages
$(objcbfs)/%.bin: $(objcbfs)/%.elf
@@ -152,7 +148,7 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug
$(OBJCOPY) --add-gnu-debuglink=$< $@.tmp
mv $@.tmp $@
-#######################################################################
+################################################################################
# Build the coreboot_ram (stage 2)
$(objcbfs)/coreboot_ram.debug: $(objgenerated)/coreboot_ram.o $(src)/arch/x86/coreboot_ram.ld
@@ -176,7 +172,7 @@ $(objgenerated)/ramstage.a: $$(ramstage-objs)
rm -f $@
$(AR) cr $@ $^
-#######################################################################
+################################################################################
# Ramstage for AP CPU (AMD K8, obsolete?)
$(objcbfs)/coreboot_ap.debug: $(objgenerated)/coreboot_ap.o $(src)/arch/x86/init/ldscript_apc.lb
@@ -187,7 +183,7 @@ $(objgenerated)/coreboot_ap.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $(
@printf " CC $(subst $(obj)/,,$(@))\n"
$(CC) -MMD $(CFLAGS) -I$(src) -D__PRE_RAM__ -I. -I$(obj) -c $< -o $@
-#######################################################################
+################################################################################
# done
crt0s = $(src)/arch/x86/init/prologue.inc
@@ -268,7 +264,7 @@ ifeq ($(CONFIG_HAVE_BUS_CONFIG),y)
ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/get_bus_conf.c
endif
-#######################################################################
+################################################################################
# Build the final rom image
$(obj)/coreboot.pre: $(objcbfs)/romstage_xip.elf $(obj)/coreboot.pre1 $(CBFSTOOL)
@@ -278,7 +274,7 @@ $(obj)/coreboot.pre: $(objcbfs)/romstage_xip.elf $(obj)/coreboot.pre1 $(CBFSTOOL
$(CONFIG_CBFS_PREFIX)/romstage x $(shell cat $(objcbfs)/base_xip.txt)
mv $@.tmp $@
-#######################################################################
+################################################################################
# Build the bootblock
bootblock_lds = $(src)/arch/x86/init/ldscript_failover.lb
@@ -335,7 +331,7 @@ else
$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld $<
endif
-#######################################################################
+################################################################################
# Build the romstage
$(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld
diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig
index baf686ea75..1ed721f7e0 100644
--- a/src/cpu/Kconfig
+++ b/src/cpu/Kconfig
@@ -62,10 +62,90 @@ config SSE2
streaming SIMD instructions. Some parts of coreboot can be built
with more efficient code if SSE2 instructions are available.
-config MICROCODE_IN_CBFS
- bool "Look for microcode in CBFS"
+endif # ARCH_X86
+
+config CPU_MICROCODE_IN_CBFS
+ bool
default n
+
+choice
+ prompt "Include CPU microcode in CBFS"
+ default CPU_MICROCODE_CBFS_GENERATE if CPU_MICROCODE_IN_CBFS
+ default CPU_MICROCODE_CBFS_NONE if !CPU_MICROCODE_IN_CBFS
+
+config CPU_MICROCODE_CBFS_GENERATE
+ bool "Generate from tree"
help
- Load microcode updates from CBFS instead of compiling them in.
+ Select this option if you want microcode updates to be assembled when
+ building coreboot and included in the final image as a separate CBFS
+ file. Microcode will not be hard-coded into ramstage.
-endif # ARCH_X86
+ The microcode file and may be removed from the ROM image at a later
+ time with cbfstool, if desired.
+
+ If unsure, select this option.
+
+config CPU_MICROCODE_CBFS_EXTERNAL
+ bool "Include external microcode file"
+ help
+ Select this option if you want to include an external file containing
+ the CPU microcode. This will be included as a separate file in CBFS.
+ A word of caution: only select this option if you are sure the
+ microcode that you have is newer than the microcode shipping with
+ coreboot.
+
+ The microcode file and may be removed from the ROM image at a later
+ time with cbfstool, if desired.
+
+ If unsure, select "Generate from tree"
+
+config CPU_MICROCODE_FILE
+ string "Path and filename of CPU microcode"
+ depends on CPU_MICROCODE_CBFS_EXTERNAL
+ default "cpu_microcode.bin"
+ help
+ The path and filename of the file containing the CPU microcode.
+
+config CPU_MICROCODE_CBFS_NONE
+ bool "Do not include microcode updates"
+ help
+ Select this option if you do not want CPU microcode included in CBFS.
+ Note that for some CPUs, the microcode is hard-coded into the source
+ tree and is not loaded from CBFS. In this case, microcode will still
+ be updated. There is a push to move all microcode to CBFS, but this
+ change is not implemented for all CPUs.
+
+ This option currently applies to:
+ - Intel SandyBridge/IvyBridge
+ - VIA Nano
+
+ Microcode may be added to the ROM image at a later time with cbfstool,
+ if desired.
+
+ If unsure, select "Generate from tree"
+
+ The GOOD:
+ Microcode updates intend to solve issues that have been discovered
+ after CPU production. The expected effect is that systems work as
+ intended with the updated microcode, but we have also seen cases where
+ issues were solved by not applying microcode updates.
+
+ The BAD:
+ Note that some operating system include these same microcode patches,
+ so you may need to also disable microcode updates in your operating
+ system for this option to have an effect.
+
+ The UGLY:
+ A word of CAUTION: some CPUs depend on microcode updates to function
+ correctly. Not updating the microcode may leave the CPU operating at
+ less than optimal performance, or may cause outright hangups.
+ There are CPUs where coreboot cannot properly initialize the CPU
+ without microcode updates
+ For example, if running with the factory microcode, some Intel
+ SandyBridge CPUs may hang when enabling CAR, or some VIA Nano CPUs
+ will hang when changing the frequency.
+
+ Make sure you have a way of flashing the ROM externally before
+ selecting this option.
+
+endchoice
diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
index 57273cf8c3..938a8dfef1 100644
--- a/src/cpu/Makefile.inc
+++ b/src/cpu/Makefile.inc
@@ -1,3 +1,40 @@
+################################################################################
+## Subdirectories
+################################################################################
subdirs-y += amd
subdirs-y += intel
subdirs-y += via
+
+################################################################################
+## Rules for building the microcode blob in CBFS
+################################################################################
+
+ifneq ($(CONFIG_CPU_MICROCODE_CBFS_NONE), y)
+
+cbfs-files-y += cpu_microcode_blob.bin
+
+cpu_microcode_blob.bin-type = 0x53
+
+# External microcode file, or are we generating one ?
+ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL), y)
+cpu_microcode_blob.bin-file = $(call strip_quotes,$(CONFIG_CPU_MICROCODE_FILE))
+else
+cpu_microcode_blob.bin-file = $(obj)/cpu_microcode_blob.bin
+endif
+
+# In case we have more than one "source" (cough) files containing microcode, we
+# Link them together in one large blob, so that we get all the microcode updates
+# in one file. This makes it easier for objcopy in the final step.
+# The --entry=0 is just here to suppress the LD warning. It does not affect the
+# final microcode file.
+$(obj)/cpu_microcode_blob.o: $$(cpu_microcode-objs)
+ @printf " LD $(subst $(obj)/,,$(@))\n"
+ $(LD) -static --entry=0 $< -o $@
+
+# We have a lot of useless data in the large blob, and we are only interested in
+# the data section, so we only copy that part to the final microcode file
+$(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o
+ @printf " MICROCODE $(subst $(obj)/,,$(@))\n"
+ $(OBJCOPY) -j .data -O binary $< $@
+
+endif
diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc
index f4d01020d1..22655c9532 100644
--- a/src/cpu/intel/microcode/Makefile.inc
+++ b/src/cpu/intel/microcode/Makefile.inc
@@ -1,15 +1,5 @@
-ramstage-y += microcode.c
-
-
-ifeq ($(CONFIG_MICROCODE_IN_CBFS),y)
-
-SRC_PATH = src/cpu/intel/microcode
-FLAGS = -I $(CONFIG_MICROCODE_INCLUDE_PATH) -include $(obj)/config.h
-$(obj)/microcode_blob.o: $(SRC_PATH)/microcode_blob.c
- $(CC) $(FLAGS) -MMD -c -o $@ $<
-
-$(obj)/microcode_blob.bin: $(obj)/microcode_blob.o
- objcopy -j .data -O binary $< $@
-
--include $(obj)/microcode_blob.d
-endif
+################################################################################
+## One small file with the awesome super-power of updating the cpu microcode
+## directly from CBFS. You have been WARNED!!!
+################################################################################
+ramstage-y += microcode.c \ No newline at end of file
diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c
index e84bad9beb..a4471ca042 100644
--- a/src/cpu/intel/microcode/microcode.c
+++ b/src/cpu/intel/microcode/microcode.c
@@ -28,7 +28,7 @@
#include <cpu/x86/msr.h>
#include <cpu/intel/microcode.h>
-#if CONFIG_MICROCODE_IN_CBFS
+#if CONFIG_CPU_MICROCODE_IN_CBFS
#ifdef __PRE_RAM__
#include <arch/cbfs.h>
#else
@@ -77,7 +77,7 @@ static inline u32 read_microcode_rev(void)
return msr.hi;
}
-#if CONFIG_MICROCODE_IN_CBFS
+#if CONFIG_CPU_MICROCODE_IN_CBFS
static
#endif
void intel_update_microcode(const void *microcode_updates)
@@ -144,9 +144,9 @@ void intel_update_microcode(const void *microcode_updates)
}
}
-#if CONFIG_MICROCODE_IN_CBFS
+#if CONFIG_CPU_MICROCODE_IN_CBFS
-#define MICROCODE_CBFS_FILE "microcode_blob.bin"
+#define MICROCODE_CBFS_FILE "cpu_microcode_blob.bin"
void intel_update_microcode_from_cbfs(void)
{
diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig
index 6635868453..5c543b88ba 100644
--- a/src/cpu/intel/model_206ax/Kconfig
+++ b/src/cpu/intel/model_206ax/Kconfig
@@ -12,7 +12,7 @@ config CPU_SPECIFIC_OPTIONS
select SSE2
select UDELAY_LAPIC
select SMM_TSEG
- select MICROCODE_IN_CBFS
+ select CPU_MICROCODE_IN_CBFS
#select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE
diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc
index e9b8e6df8e..6ab4840c48 100644
--- a/src/cpu/intel/model_206ax/Makefile.inc
+++ b/src/cpu/intel/model_206ax/Makefile.inc
@@ -5,4 +5,6 @@ ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
+cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
+
cpu_incs += $(src)/cpu/intel/model_206ax/cache_as_ram.inc
diff --git a/src/cpu/intel/microcode/microcode_blob.c b/src/cpu/intel/model_206ax/microcode_blob.c
index 69238a9f77..c2538e8ede 100644
--- a/src/cpu/intel/microcode/microcode_blob.c
+++ b/src/cpu/intel/model_206ax/microcode_blob.c
@@ -18,5 +18,5 @@
*/
unsigned microcode[] = {
-#include <microcode_blob.h>
+#include "microcode_blob.h"
};
diff --git a/src/include/cpu/intel/microcode.h b/src/include/cpu/intel/microcode.h
index 289e9196fa..e9c13f978c 100644
--- a/src/include/cpu/intel/microcode.h
+++ b/src/include/cpu/intel/microcode.h
@@ -21,7 +21,7 @@
#define __CPU__INTEL__MICROCODE__
#ifndef __PRE_RAM__
-#if CONFIG_MICROCODE_IN_CBFS
+#if CONFIG_CPU_MICROCODE_IN_CBFS
void intel_update_microcode_from_cbfs(void);
#else
void intel_update_microcode(const void *microcode_updates);