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-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb3
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb3
2 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index 612a97d201..b4a121a95a 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -114,6 +114,9 @@ chip soc/intel/tigerlake
register "TcssXhciEn" = "1"
register "TcssAuxOri" = "0"
+ # Enable S0ix
+ register "s0ix_enable" = "1"
+
# D3Hot and D3Cold for TCSS
register "TcssD3HotEnable" = "1"
register "TcssD3ColdEnable" = "1"
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index 7a97ad9098..b08cd3c119 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -110,6 +110,9 @@ chip soc/intel/tigerlake
register "TcssXhciEn" = "1"
register "TcssAuxOri" = "0"
+ # Enable S0ix
+ register "s0ix_enable" = "1"
+
# D3Hot and D3Cold for TCSS
register "TcssD3HotEnable" = "1"
register "TcssD3ColdEnable" = "1"