diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/apollolake/Kconfig | 3 | ||||
| -rw-r--r-- | src/soc/intel/common/Kconfig | 15 | ||||
| -rw-r--r-- | src/soc/intel/common/lpss_i2c.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/common/lpss_i2c.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/skylake/Kconfig | 8 |
5 files changed, 14 insertions, 16 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index ca8f5d0829..70d2099605 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -117,8 +117,7 @@ config CPU_ADDR_BITS int default 36 -config SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ - depends on SOC_INTEL_COMMON_LPSS_I2C +config SOC_INTEL_COMMON_LPSS_CLOCK_MHZ int default 133 diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 3d2ced95d6..919cb50406 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -67,6 +67,13 @@ config ACPI_CONSOLE help Provide a mechanism for serial console based ACPI debug. +config SOC_INTEL_COMMON_LPSS_CLOCK_MHZ + int + help + The clock speed that the controllers in LPSS(GSPI, I2C) are running + at, in MHz. No default is set here as this is an SOC-specific value + and must be provided by the SOC. + config SOC_INTEL_COMMON_LPSS_I2C bool default n @@ -74,14 +81,6 @@ config SOC_INTEL_COMMON_LPSS_I2C This driver supports the Intel Low Power Subsystem (LPSS) I2C controllers that are based on Synopsys DesignWare IP. -config SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ - int - depends on SOC_INTEL_COMMON_LPSS_I2C - help - The clock speed that the I2C controller is running at, in MHz. - No default is set here as this is an SOC-specific value and must - be provided by the SOC when it selects this driver. - config SOC_INTEL_COMMON_LPSS_I2C_DEBUG bool "Enable debug output for LPSS I2C transactions" default n diff --git a/src/soc/intel/common/lpss_i2c.c b/src/soc/intel/common/lpss_i2c.c index 19fda4c703..b61c24afd7 100644 --- a/src/soc/intel/common/lpss_i2c.c +++ b/src/soc/intel/common/lpss_i2c.c @@ -611,7 +611,7 @@ static int lpss_i2c_gen_speed_config(struct lpss_i2c_regs *regs, const struct lpss_i2c_bus_config *bcfg, struct lpss_i2c_speed_config *config) { - const int ic_clk = CONFIG_SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ; + const int ic_clk = CONFIG_SOC_INTEL_COMMON_LPSS_CLOCK_MHZ; uint16_t hcnt_min, lcnt_min; int i; diff --git a/src/soc/intel/common/lpss_i2c.h b/src/soc/intel/common/lpss_i2c.h index b9517701f6..b46e657fd6 100644 --- a/src/soc/intel/common/lpss_i2c.h +++ b/src/soc/intel/common/lpss_i2c.h @@ -21,7 +21,7 @@ /* * Timing values are in units of clock period, with the clock speed - * provided by the SOC in CONFIG_SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ. + * provided by the SOC in CONFIG_SOC_INTEL_COMMON_LPSS_CLOCK_MHZ. * Automatic configuration is done based on requested speed, but the * values may need tuned depending on the board and the number of * devices present on the bus. diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 8ac7263c89..df8ae2bd2d 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -109,10 +109,6 @@ config CPU_ADDR_BITS int default 36 -config SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ - int - default 120 - config DCACHE_RAM_BASE hex "Base address of cache-as-RAM" default 0xfef00000 @@ -300,4 +296,8 @@ config NO_FADT_8042 help Choose this option if you want to disable 8042 Keyboard +config SOC_INTEL_COMMON_LPSS_CLOCK_MHZ + int + default 120 + endif |