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-rw-r--r--src/northbridge/amd/agesa/eventlog.c2
-rw-r--r--src/northbridge/amd/amdk8/exit_from_self.c2
-rw-r--r--src/northbridge/amd/amdmct/mct/mct_d.c6
-rw-r--r--src/northbridge/amd/amdmct/mct/mctdqs_d.c2
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mct_d.c4
-rw-r--r--src/northbridge/intel/i945/raminit.c10
-rw-r--r--src/northbridge/via/vx900/northbridge.c4
7 files changed, 15 insertions, 15 deletions
diff --git a/src/northbridge/amd/agesa/eventlog.c b/src/northbridge/amd/agesa/eventlog.c
index 6c219edc3c..0a40672960 100644
--- a/src/northbridge/amd/agesa/eventlog.c
+++ b/src/northbridge/amd/agesa/eventlog.c
@@ -555,7 +555,7 @@ static void agesa_critical(EVENT_PARAMS *event)
break;
case HT_EVENT_COH_PROCESSOR_TYPE_MIX:
- printk(BIOS_DEBUG, "Socket %x Link %x TotalSockets %x, HT_EVENT_COH_PROCESSOR_TYPE_MIX \n",
+ printk(BIOS_DEBUG, "Socket %x Link %x TotalSockets %x, HT_EVENT_COH_PROCESSOR_TYPE_MIX\n",
(unsigned int)event->DataParam1,
(unsigned int)event->DataParam2,
(unsigned int)event->DataParam3);
diff --git a/src/northbridge/amd/amdk8/exit_from_self.c b/src/northbridge/amd/amdk8/exit_from_self.c
index 639eac7fa2..858a0c0a3f 100644
--- a/src/northbridge/amd/amdk8/exit_from_self.c
+++ b/src/northbridge/amd/amdk8/exit_from_self.c
@@ -116,7 +116,7 @@ void exit_from_self(int controllers, const struct mem_controller *ctrl,
"orb %1, %%al\n\t"
"not %1\n\t"
".align 64\n\t"
- "outl %%eax, (%%dx) \n\t"
+ "outl %%eax, (%%dx)\n\t"
"andb %1, %%al\n\t"
"outl %%eax, (%%dx)\n\t"
"popl %0\n\t"::"a"(pcidev),
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c
index 0e59e1d2a0..0914065d2a 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct/mct_d.c
@@ -644,7 +644,7 @@ static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat,
devx = pDCTstat->dev_map;
if (pDCTstat->NodePresent) {
- printk(BIOS_DEBUG, " Copy dram map from Node 0 to Node %02x \n", Node);
+ printk(BIOS_DEBUG, " Copy dram map from Node 0 to Node %02x\n", Node);
reg = 0x40; /*Dram Base 0*/
do {
val = Get_NB32(dev, reg);
@@ -892,7 +892,7 @@ static void StartupDCT_D(struct MCTStatStruc *pMCTstat,
byte = mctGet_NVbits(NV_DQSTrainCTL);
if (byte == 1) {
/* Enable DQSRcvEn training mode */
- print_t("\t\t\tStartupDCT_D: DqsRcvEnTrain set \n");
+ print_t("\t\t\tStartupDCT_D: DqsRcvEnTrain set\n");
reg = 0x78 + reg_off;
val = Get_NB32(dev, reg);
/* Setting this bit forces a 1T window with hard left
@@ -903,7 +903,7 @@ static void StartupDCT_D(struct MCTStatStruc *pMCTstat,
Set_NB32(dev, reg, val);
}
mctHookBeforeDramInit(); /* generalized Hook */
- print_t("\t\t\tStartupDCT_D: DramInit \n");
+ print_t("\t\t\tStartupDCT_D: DramInit\n");
mct_DramInit(pMCTstat, pDCTstat, dct);
AfterDramInit_D(pDCTstat, dct);
mctHookAfterDramInit(); /* generalized Hook*/
diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
index f8784aff68..abc5838c54 100644
--- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
@@ -511,7 +511,7 @@ static void TrainDQSPos_D(struct MCTStatStruc *pMCTstat,
}
MutualCSPassW[DQSDelay] &= tmp;
- print_debug_dqs("\t\t\t\t\tTrainDQSPos: 146 \tMutualCSPassW ", MutualCSPassW[DQSDelay], 5);
+ print_debug_dqs("\t\t\t\t\tTrainDQSPos: 146\tMutualCSPassW ", MutualCSPassW[DQSDelay], 5);
SetTargetWTIO_D(TestAddr);
FlushDQSTestPattern_D(pDCTstat, TestAddr << 8);
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index 4fa7e66ae3..7aee892b36 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -3973,7 +3973,7 @@ static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat,
val |= Node;
Set_NB32(dev, 0x44 + (Node << 3), val); /* set DstNode */
- printk(BIOS_DEBUG, " Node: %02x base: %02x limit: %02x \n", Node, base, limit);
+ printk(BIOS_DEBUG, " Node: %02x base: %02x limit: %02x\n", Node, base, limit);
limit = pDCTstat->DCTSysLimit;
if (limit) {
NextBase = (limit & 0xFFFF0000) + 0x10000;
@@ -3987,7 +3987,7 @@ static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat,
devx = pDCTstat->dev_map;
if (pDCTstat->NodePresent) {
- printk(BIOS_DEBUG, " Copy dram map from Node 0 to Node %02x \n", Node);
+ printk(BIOS_DEBUG, " Copy dram map from Node 0 to Node %02x\n", Node);
reg = 0x40; /*Dram Base 0*/
do {
val = Get_NB32(dev, reg);
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 5469059070..27acef3365 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -1235,7 +1235,7 @@ static void sdram_program_dll_timings(struct sys_info *sysinfo)
u32 chan0dll = 0, chan1dll = 0;
int i;
- printk(BIOS_DEBUG, "Programming DLL Timings... \n");
+ printk(BIOS_DEBUG, "Programming DLL Timings...\n");
MCHBAR16(DQSMT) &= ~( (3 << 12) | (1 << 10) | ( 0xf << 0) );
MCHBAR16(DQSMT) |= (1 << 13) | (0xc << 0);
@@ -1287,7 +1287,7 @@ static void sdram_initialize_system_memory_io(struct sys_info *sysinfo)
u8 reg8;
u32 reg32;
- printk(BIOS_DEBUG, "Initializing System Memory IO... \n");
+ printk(BIOS_DEBUG, "Initializing System Memory IO...\n");
/* Enable Data Half Clock Pushout */
reg8 = MCHBAR8(C0HCTC);
reg8 &= ~0x1f;
@@ -1329,7 +1329,7 @@ static void sdram_enable_system_memory_io(struct sys_info *sysinfo)
{
u32 reg32;
- printk(BIOS_DEBUG, "Enabling System Memory IO... \n");
+ printk(BIOS_DEBUG, "Enabling System Memory IO...\n");
reg32 = MCHBAR32(RCVENMT);
reg32 &= ~(0x3f << 6);
@@ -1561,7 +1561,7 @@ static int sdram_set_row_attributes(struct sys_info *sysinfo)
int i, value;
u16 dra0=0, dra1=0, dra = 0;
- printk(BIOS_DEBUG, "Setting row attributes... \n");
+ printk(BIOS_DEBUG, "Setting row attributes...\n");
for(i=0; i < 2 * DIMM_SOCKETS; i++) {
u16 device;
u8 columnsrows;
@@ -2763,7 +2763,7 @@ static void sdram_on_die_termination(struct sys_info *sysinfo)
if ( !(sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED &&
sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) ) {
- printk(BIOS_DEBUG, "one dimm per channel config.. \n");
+ printk(BIOS_DEBUG, "one dimm per channel config..\n");
reg32 = MCHBAR32(C0ODT);
reg32 &= ~(7 << 28);
diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c
index 32bb539812..a4a8ecec48 100644
--- a/src/northbridge/via/vx900/northbridge.c
+++ b/src/northbridge/via/vx900/northbridge.c
@@ -82,8 +82,8 @@ static void killme_debug_4g_remap_reg(u32 reg32)
u64 remapend = (reg32 >> 14) & 0x3ff;
remapstart <<= 26;
remapend <<= 26;
- printk(BIOS_DEBUG, "Remapstart %lld(MB) \n", remapstart >> 20);
- printk(BIOS_DEBUG, "Remapend %lld(MB) \n", remapend >> 20);
+ printk(BIOS_DEBUG, "Remapstart %lld(MB)\n", remapstart >> 20);
+ printk(BIOS_DEBUG, "Remapend %lld(MB)\n", remapend >> 20);
}
/**
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-07 19:26:21 +0000