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-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c18
1 files changed, 18 insertions, 0 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
index d1dc4ca251..8638b806b6 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
@@ -32,6 +32,24 @@ static const struct pad_config gpio_table[] = {
/* Image clock: IMGCLKOUT_0, IMGCLKOUT_1 */
PAD_CFG_NF(GPP_D4, NONE, PLTRST, NF1),
PAD_CFG_NF(GPP_H20, NONE, PLTRST, NF1),
+
+ /* ISH UART0 RX/TX */
+ PAD_CFG_NF(GPP_D13, NONE, PLTRST, NF1),
+ PAD_CFG_NF(GPP_D14, NONE, PLTRST, NF1),
+
+ /* ISH I2C0 */
+ PAD_CFG_NF(GPP_B5, NONE, PLTRST, NF1),
+ PAD_CFG_NF(GPP_B6, NONE, PLTRST, NF1),
+
+ /* ISH GPI 0-6 */
+ PAD_CFG_NF(GPP_D0, NONE, PLTRST, NF1),
+ PAD_CFG_NF(GPP_D1, NONE, PLTRST, NF1),
+ PAD_CFG_NF(GPP_D2, NONE, PLTRST, NF1),
+ PAD_CFG_NF(GPP_D3, NONE, PLTRST, NF1),
+ PAD_CFG_NF(GPP_D17, NONE, PLTRST, NF1),
+ PAD_CFG_NF(GPP_D18, NONE, PLTRST, NF1),
+ PAD_CFG_NF(GPP_E15, NONE, PLTRST, NF1),
+ PAD_CFG_NF(GPP_E16, NONE, PLTRST, NF1),
};
/* Early pad configuration in bootblock */