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-rw-r--r--src/soc/intel/xeon_sp/cpx/cpu.c31
-rw-r--r--src/soc/intel/xeon_sp/cpx/include/soc/cpu.h2
-rw-r--r--src/soc/intel/xeon_sp/skx/cpu.c31
-rw-r--r--src/soc/intel/xeon_sp/skx/include/soc/cpu.h2
4 files changed, 66 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c
index 386401f7e3..1df5c1350c 100644
--- a/src/soc/intel/xeon_sp/cpx/cpu.c
+++ b/src/soc/intel/xeon_sp/cpx/cpu.c
@@ -188,3 +188,34 @@ void cpx_init_cpus(struct device *dev)
/* update numa domain for all cpu devices */
xeonsp_init_cpu_config();
}
+
+msr_t read_msr_ppin(void)
+{
+ msr_t ppin = {0};
+ msr_t msr;
+
+ /* If MSR_PLATFORM_INFO PPIN_CAP is 0, PPIN capability is not supported */
+ msr = rdmsr(MSR_PLATFORM_INFO);
+ if ((msr.lo & MSR_PPIN_CAP) == 0) {
+ printk(BIOS_ERR, "MSR_PPIN_CAP is 0, PPIN is not supported\n");
+ return ppin;
+ }
+
+ /* Access to MSR_PPIN is permitted only if MSR_PPIN_CTL LOCK is 0 and ENABLE is 1 */
+ msr = rdmsr(MSR_PPIN_CTL);
+ if (msr.lo & MSR_PPIN_CTL_LOCK) {
+ printk(BIOS_ERR, "MSR_PPIN_CTL_LOCK is 1, PPIN access is not allowed\n");
+ return ppin;
+ }
+
+ if ((msr.lo & MSR_PPIN_CTL_ENABLE) == 0) {
+ /* Set MSR_PPIN_CTL ENABLE to 1 */
+ msr.lo |= MSR_PPIN_CTL_ENABLE;
+ wrmsr(MSR_PPIN_CTL, msr);
+ }
+ ppin = rdmsr(MSR_PPIN);
+ /* Set enable to 0 after reading MSR_PPIN */
+ msr.lo &= ~MSR_PPIN_CTL_ENABLE;
+ wrmsr(MSR_PPIN_CTL, msr);
+ return ppin;
+}
diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h
index 2d1269949c..14580004d0 100644
--- a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h
+++ b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h
@@ -4,6 +4,7 @@
#define _SOC_CPU_H
#include <device/device.h>
+#include <cpu/x86/msr.h>
#define CPUID_COOPERLAKE_SP_A0 0x05065a
@@ -11,5 +12,6 @@
#define CPU_BCLK 100
void cpx_init_cpus(struct device *dev);
+msr_t read_msr_ppin(void);
#endif
diff --git a/src/soc/intel/xeon_sp/skx/cpu.c b/src/soc/intel/xeon_sp/skx/cpu.c
index f97c37da08..c59edab0bb 100644
--- a/src/soc/intel/xeon_sp/skx/cpu.c
+++ b/src/soc/intel/xeon_sp/skx/cpu.c
@@ -244,3 +244,34 @@ void xeon_sp_init_cpus(struct device *dev)
FUNC_EXIT();
}
+
+msr_t read_msr_ppin(void)
+{
+ msr_t ppin = {0};
+ msr_t msr;
+
+ /* If MSR_PLATFORM_INFO PPIN_CAP is 0, PPIN capability is not supported */
+ msr = rdmsr(MSR_PLATFORM_INFO);
+ if ((msr.lo & MSR_PPIN_CAP) == 0) {
+ printk(BIOS_ERR, "MSR_PPIN_CAP is 0, PPIN is not supported\n");
+ return ppin;
+ }
+
+ /* Access to MSR_PPIN is permitted only if MSR_PPIN_CTL LOCK is 0 and ENABLE is 1 */
+ msr = rdmsr(MSR_PPIN_CTL);
+ if (msr.lo & MSR_PPIN_CTL_LOCK) {
+ printk(BIOS_ERR, "MSR_PPIN_CTL_LOCK is 1, PPIN access is not allowed\n");
+ return ppin;
+ }
+
+ if ((msr.lo & MSR_PPIN_CTL_ENABLE) == 0) {
+ /* Set MSR_PPIN_CTL ENABLE to 1 */
+ msr.lo |= MSR_PPIN_CTL_ENABLE;
+ wrmsr(MSR_PPIN_CTL, msr);
+ }
+ ppin = rdmsr(MSR_PPIN);
+ /* Set enable to 0 after reading MSR_PPIN */
+ msr.lo &= ~MSR_PPIN_CTL_ENABLE;
+ wrmsr(MSR_PPIN_CTL, msr);
+ return ppin;
+}
diff --git a/src/soc/intel/xeon_sp/skx/include/soc/cpu.h b/src/soc/intel/xeon_sp/skx/include/soc/cpu.h
index 0221c7d057..c2af265b91 100644
--- a/src/soc/intel/xeon_sp/skx/include/soc/cpu.h
+++ b/src/soc/intel/xeon_sp/skx/include/soc/cpu.h
@@ -4,6 +4,7 @@
#define _SOC_CPU_H_
#include <device/device.h>
+#include <cpu/x86/msr.h>
/* SKXSP CPUID */
#define CPUID_SKYLAKE_SP_A0_A1 0x506f0
@@ -15,5 +16,6 @@
int get_cpu_count(void);
void xeon_sp_init_cpus(struct device *dev);
+msr_t read_msr_ppin(void);
#endif