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-rw-r--r--src/cpu/allwinner/a10/Kconfig1
-rw-r--r--src/cpu/ti/am335x/Kconfig1
-rw-r--r--src/drivers/uart/Kconfig8
-rw-r--r--src/drivers/uart/oxpcie_early.c5
-rw-r--r--src/drivers/uart/pl011.c5
-rw-r--r--src/drivers/uart/uart8250io.c17
-rw-r--r--src/drivers/uart/uart8250mem.c5
-rw-r--r--src/drivers/uart/util.c16
-rw-r--r--src/soc/imgtec/pistachio/Kconfig1
-rw-r--r--src/soc/intel/apollolake/uart_early.c6
-rw-r--r--src/soc/intel/quark/Kconfig1
-rw-r--r--src/soc/intel/skylake/uart_debug.c11
-rw-r--r--src/soc/marvell/armada38x/Kconfig1
-rw-r--r--src/soc/nvidia/tegra132/Kconfig1
-rw-r--r--src/soc/rockchip/rk3288/Kconfig1
-rw-r--r--src/soc/rockchip/rk3399/Kconfig1
-rw-r--r--src/southbridge/amd/pi/hudson/Kconfig1
17 files changed, 38 insertions, 44 deletions
diff --git a/src/cpu/allwinner/a10/Kconfig b/src/cpu/allwinner/a10/Kconfig
index 814b69e1f0..0e5aba98b7 100644
--- a/src/cpu/allwinner/a10/Kconfig
+++ b/src/cpu/allwinner/a10/Kconfig
@@ -13,5 +13,6 @@ config CPU_SPECIFIC_OPTIONS
select HAVE_MONOTONIC_TIMER
select HAVE_UART_SPECIAL
select BOOTBLOCK_CONSOLE
+ select UART_OVERRIDE_REFCLK
endif # if CPU_ALLWINNER_A10
diff --git a/src/cpu/ti/am335x/Kconfig b/src/cpu/ti/am335x/Kconfig
index 8d3c691161..f44c69d686 100644
--- a/src/cpu/ti/am335x/Kconfig
+++ b/src/cpu/ti/am335x/Kconfig
@@ -7,5 +7,6 @@ config CPU_TI_AM335X
select HAVE_UART_SPECIAL
select BOOTBLOCK_CONSOLE
select GENERIC_UDELAY
+ select UART_OVERRIDE_REFCLK
bool
default n
diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig
index cb129b0643..4faa48d9f0 100644
--- a/src/drivers/uart/Kconfig
+++ b/src/drivers/uart/Kconfig
@@ -20,6 +20,13 @@ config UART_OVERRIDE_INPUT_CLOCK_DIVIDER
Set to "y" when the platform overrides the uart_input_clock_divider
routine.
+config UART_OVERRIDE_REFCLK
+ boolean
+ default n
+ help
+ Set to "y" when the platform overrides the uart_platform_refclk
+ routine.
+
config DRIVERS_UART_8250MEM
bool
default n
@@ -39,6 +46,7 @@ config DRIVERS_UART_OXPCIE
depends on PCI
select DRIVERS_UART_8250MEM
select EARLY_PCI_BRIDGE
+ select UART_OVERRIDE_REFCLK
help
Support for Oxford OXPCIe952 serial port PCIe cards.
Currently only devices with the vendor ID 0x1415 and device ID
diff --git a/src/drivers/uart/oxpcie_early.c b/src/drivers/uart/oxpcie_early.c
index 6582a9e5ab..0a778d98c7 100644
--- a/src/drivers/uart/oxpcie_early.c
+++ b/src/drivers/uart/oxpcie_early.c
@@ -92,10 +92,7 @@ void uart_fill_lb(void *data)
serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
serial.baud = default_baudrate();
serial.regwidth = 1;
- if (IS_ENABLED(CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK))
- serial.input_hertz = uart_platform_refclk();
- else
- serial.input_hertz = 0;
+ serial.input_hertz = uart_platform_refclk();
serial.uart_pci_addr = CONFIG_UART_PCI_ADDR;
lb_add_serial(&serial, data);
diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c
index 808cb46538..0c7ac08ed5 100644
--- a/src/drivers/uart/pl011.c
+++ b/src/drivers/uart/pl011.c
@@ -48,10 +48,7 @@ void uart_fill_lb(void *data)
serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
serial.baud = default_baudrate();
serial.regwidth = 1;
- if (IS_ENABLED(CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK))
- serial.input_hertz = uart_platform_refclk();
- else
- serial.input_hertz = 0;
+ serial.input_hertz = uart_platform_refclk();
serial.uart_pci_addr = CONFIG_UART_PCI_ADDR;
lb_add_serial(&serial, data);
diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c
index 69244f58df..89c447658a 100644
--- a/src/drivers/uart/uart8250io.c
+++ b/src/drivers/uart/uart8250io.c
@@ -27,16 +27,6 @@
/* Should support 8250, 16450, 16550, 16550A type UARTs */
-/* Nominal values only, good for the range of choices Kconfig offers for
- * set of standard baudrates.
- */
-
-/* Multiply the maximim baud-rate by the default oversample rate to compute
- * the default input clock to the UART. The uart_baudrate_divisor divides
- * by the oversample clock to determine the final baud-rate.
- */
-#define BAUDRATE_REFCLK (115200 * 16)
-
/* Expected character delay at 1200bps is 9ms for a working UART
* and no flow-control. Assume UART as stuck if shift register
* or FIFO takes more than 50ms per character to appear empty.
@@ -115,7 +105,7 @@ uintptr_t uart_platform_base(int idx)
void uart_init(int idx)
{
unsigned int div;
- div = uart_baudrate_divisor(default_baudrate(), BAUDRATE_REFCLK,
+ div = uart_baudrate_divisor(default_baudrate(), uart_platform_refclk(),
uart_input_clock_divider());
uart8250_init(uart_platform_base(idx), div);
}
@@ -143,10 +133,7 @@ void uart_fill_lb(void *data)
serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
serial.baud = default_baudrate();
serial.regwidth = 1;
- if (IS_ENABLED(CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK))
- serial.input_hertz = uart_platform_refclk();
- else
- serial.input_hertz = 0;
+ serial.input_hertz = uart_platform_refclk();
serial.uart_pci_addr = CONFIG_UART_PCI_ADDR;
lb_add_serial(&serial, data);
diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c
index 4b87756d0b..cf58423b86 100644
--- a/src/drivers/uart/uart8250mem.c
+++ b/src/drivers/uart/uart8250mem.c
@@ -157,10 +157,7 @@ void uart_fill_lb(void *data)
serial.regwidth = sizeof(uint32_t);
else
serial.regwidth = sizeof(uint8_t);
- if (IS_ENABLED(CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK))
- serial.input_hertz = uart_platform_refclk();
- else
- serial.input_hertz = 0;
+ serial.input_hertz = uart_platform_refclk();
serial.uart_pci_addr = CONFIG_UART_PCI_ADDR;
lb_add_serial(&serial, data);
diff --git a/src/drivers/uart/util.c b/src/drivers/uart/util.c
index 5e8d223252..86da8dc746 100644
--- a/src/drivers/uart/util.c
+++ b/src/drivers/uart/util.c
@@ -59,3 +59,19 @@ unsigned int uart_input_clock_divider(void)
return 16;
}
#endif
+
+#if !IS_ENABLED(CONFIG_UART_OVERRIDE_REFCLK)
+unsigned int uart_platform_refclk(void)
+{
+ /* Specify the default input clock frequency for the UART.
+ *
+ * The older UART's used an input clock frequency of 1.8432 MHz which
+ * with the 16x oversampling provided the maximum baud-rate of 115200.
+ * Specify this as maximum baud-rate multiplied by oversample so that
+ * it is obvious that the maximum baud rate is 115200 when divided by
+ * oversample clock. Also note that crystal on the board does not
+ * change when software selects another input clock divider.
+ */
+ return 115200 * 16;
+}
+#endif
diff --git a/src/soc/imgtec/pistachio/Kconfig b/src/soc/imgtec/pistachio/Kconfig
index 5ea6b95107..da33cc5c96 100644
--- a/src/soc/imgtec/pistachio/Kconfig
+++ b/src/soc/imgtec/pistachio/Kconfig
@@ -25,6 +25,7 @@ config CPU_IMGTEC_PISTACHIO
select SPI_ATOMIC_SEQUENCING
select GENERIC_GPIO_LIB
select HAVE_HARD_RESET
+ select UART_OVERRIDE_REFCLK
bool
if CPU_IMGTEC_PISTACHIO
diff --git a/src/soc/intel/apollolake/uart_early.c b/src/soc/intel/apollolake/uart_early.c
index e8dfeda565..0e530609bd 100644
--- a/src/soc/intel/apollolake/uart_early.c
+++ b/src/soc/intel/apollolake/uart_early.c
@@ -68,12 +68,6 @@ uintptr_t uart_platform_base(int idx)
return (CONFIG_CONSOLE_UART_BASE_ADDRESS);
}
-unsigned int uart_platform_refclk(void)
-{
- /* That's within 0.5% of the actual value we've set earlier */
- return 115200 * 16;
-}
-
static const struct pad_config uart_gpios[] = {
PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* UART1 RX */
PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* UART1 TX */
diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig
index ae25c328c6..6a2349fb8d 100644
--- a/src/soc/intel/quark/Kconfig
+++ b/src/soc/intel/quark/Kconfig
@@ -30,6 +30,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON
select SOC_SETS_MTRRS
select TSC_CONSTANT_RATE
+ select UART_OVERRIDE_REFCLK
select UDELAY_TSC
select UNCOMPRESSED_RAMSTAGE
select USE_MARCH_586
diff --git a/src/soc/intel/skylake/uart_debug.c b/src/soc/intel/skylake/uart_debug.c
index c463bea145..f3d576b3aa 100644
--- a/src/soc/intel/skylake/uart_debug.c
+++ b/src/soc/intel/skylake/uart_debug.c
@@ -18,17 +18,6 @@
#include <soc/iomap.h>
#include <soc/serialio.h>
-unsigned int uart_platform_refclk(void)
-{
- /*
- * Set M and N divisor inputs and enable clock.
- * Main reference frequency to UART is:
- * 120MHz * M / N = 120MHz * 48 / 3125 = 1843200Hz
- * The different order below is to handle integer math overflow.
- */
- return 120 * MHz / SIO_REG_PPR_CLOCK_N_DIV * SIO_REG_PPR_CLOCK_M_DIV;
-}
-
uintptr_t uart_platform_base(int idx)
{
/* Same base address for all debug port usage. In reality UART2
diff --git a/src/soc/marvell/armada38x/Kconfig b/src/soc/marvell/armada38x/Kconfig
index 6754a0f1f6..ed8cbe8100 100644
--- a/src/soc/marvell/armada38x/Kconfig
+++ b/src/soc/marvell/armada38x/Kconfig
@@ -10,6 +10,7 @@ config SOC_MARVELL_ARMADA38X
select RETURN_FROM_VERSTAGE
select BOOTBLOCK_CUSTOM
select GENERIC_UDELAY
+ select UART_OVERRIDE_REFCLK
if SOC_MARVELL_ARMADA38X
diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig
index 502e7c4c72..08ed47567b 100644
--- a/src/soc/nvidia/tegra132/Kconfig
+++ b/src/soc/nvidia/tegra132/Kconfig
@@ -13,6 +13,7 @@ config SOC_NVIDIA_TEGRA132
select HAVE_HARD_RESET
select HAVE_UART_SPECIAL
select GENERIC_GPIO_LIB
+ select UART_OVERRIDE_REFCLK
if SOC_NVIDIA_TEGRA132
diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig
index 8b15d3dc45..0f394b18b4 100644
--- a/src/soc/rockchip/rk3288/Kconfig
+++ b/src/soc/rockchip/rk3288/Kconfig
@@ -27,6 +27,7 @@ config SOC_ROCKCHIP_RK3288
select UNCOMPRESSED_RAMSTAGE
select GENERIC_GPIO_LIB
select RTC
+ select UART_OVERRIDE_REFCLK
if SOC_ROCKCHIP_RK3288
diff --git a/src/soc/rockchip/rk3399/Kconfig b/src/soc/rockchip/rk3399/Kconfig
index 43bb03bd4e..38d0f00413 100644
--- a/src/soc/rockchip/rk3399/Kconfig
+++ b/src/soc/rockchip/rk3399/Kconfig
@@ -12,6 +12,7 @@ config SOC_ROCKCHIP_RK3399
select GENERIC_UDELAY
select HAVE_MONOTONIC_TIMER
select UNCOMPRESSED_RAMSTAGE
+ select UART_OVERRIDE_REFCLK
if SOC_ROCKCHIP_RK3399
diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig
index aa55339ea0..8fe3b2d897 100644
--- a/src/southbridge/amd/pi/hudson/Kconfig
+++ b/src/southbridge/amd/pi/hudson/Kconfig
@@ -235,6 +235,7 @@ config HUDSON_UART
select DRIVERS_UART_8250MEM
select DRIVERS_UART_8250MEM_32
select NO_UART_ON_SUPERIO
+ select UART_OVERRIDE_REFCLK
help
There are two UART controllers in Kern.
The UART registers are memory-mapped. UART
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 19:48:00 +0000