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-rw-r--r--src/drivers/intel/fsp1_1/Kconfig1
-rw-r--r--src/drivers/intel/fsp1_1/Makefile.inc4
-rw-r--r--src/drivers/intel/fsp1_1/fsp_gop.c2
-rw-r--r--src/drivers/intel/fsp1_1/fsp_relocate.c3
-rw-r--r--src/drivers/intel/fsp1_1/fsp_util.c2
-rw-r--r--src/drivers/intel/fsp1_1/hob.c2
-rw-r--r--src/drivers/intel/fsp1_1/include/fsp/api.h41
-rw-r--r--src/drivers/intel/fsp1_1/include/fsp/gop.h (renamed from src/drivers/intel/fsp1_1/fsp_gop.h)4
-rw-r--r--src/drivers/intel/fsp1_1/include/fsp/soc_binding.h43
-rw-r--r--src/drivers/intel/fsp1_1/include/fsp/uefi_binding.h39
-rw-r--r--src/drivers/intel/fsp1_1/include/fsp/util.h (renamed from src/drivers/intel/fsp1_1/fsp_util.h)36
-rw-r--r--src/soc/intel/braswell/Makefile.inc8
-rw-r--r--src/soc/intel/braswell/acpi.c2
-rw-r--r--src/soc/intel/braswell/chip.c2
-rw-r--r--src/soc/intel/braswell/chip.h2
-rw-r--r--src/soc/intel/braswell/include/soc/chipset_fsp_util.h41
-rw-r--r--src/soc/intel/braswell/include/soc/romstage.h2
-rw-r--r--src/soc/intel/braswell/northcluster.c2
-rw-r--r--src/soc/intel/braswell/ramstage.c2
-rw-r--r--src/soc/intel/braswell/romstage/romstage.c2
-rw-r--r--src/soc/intel/common/fsp_ramstage.c2
-rw-r--r--src/soc/intel/common/raminit.c2
-rw-r--r--src/soc/intel/common/ramstage.h2
-rw-r--r--src/soc/intel/common/romstage.h2
-rw-r--r--src/soc/intel/common/vbt.c2
-rw-r--r--src/soc/intel/skylake/Makefile.inc9
-rw-r--r--src/soc/intel/skylake/chip.c2
-rw-r--r--src/soc/intel/skylake/include/soc/chipset_fsp_util.h41
-rw-r--r--src/soc/intel/skylake/ramstage.c3
-rw-r--r--src/vendorcode/intel/Kconfig3
-rw-r--r--src/vendorcode/intel/Makefile.inc10
-rw-r--r--src/vendorcode/intel/edk2/uefi_2.4/uefi_types.h18
32 files changed, 183 insertions, 153 deletions
diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig
index 2ffa323253..d23d9666f0 100644
--- a/src/drivers/intel/fsp1_1/Kconfig
+++ b/src/drivers/intel/fsp1_1/Kconfig
@@ -19,6 +19,7 @@
config PLATFORM_USES_FSP1_1
bool
+ select UEFI_2_4_BINDING
help
Does the code require the Intel Firmware Support Package?
diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc
index f831f9d696..bab68e142d 100644
--- a/src/drivers/intel/fsp1_1/Makefile.inc
+++ b/src/drivers/intel/fsp1_1/Makefile.inc
@@ -26,7 +26,9 @@ ramstage-y += fsp_relocate.c
ramstage-y += fsp_util.c
ramstage-y += hob.c
-CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1
+CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1/include
+# Where FspUpdVpd.h can be picked up from.
+CPPFLAGS_common += -I$(CONFIG_FSP_INCLUDE_PATH)
cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_1/cache_as_ram.inc
diff --git a/src/drivers/intel/fsp1_1/fsp_gop.c b/src/drivers/intel/fsp1_1/fsp_gop.c
index ed1f1b4057..c5b515c1b3 100644
--- a/src/drivers/intel/fsp1_1/fsp_gop.c
+++ b/src/drivers/intel/fsp1_1/fsp_gop.c
@@ -19,7 +19,7 @@
#include <cbfs.h>
#include <console/console.h>
-#include "fsp_util.h"
+#include <fsp/util.h>
#include <lib.h>
/* Reading VBT table from flash */
diff --git a/src/drivers/intel/fsp1_1/fsp_relocate.c b/src/drivers/intel/fsp1_1/fsp_relocate.c
index 3e526086e2..2cc2560d33 100644
--- a/src/drivers/intel/fsp1_1/fsp_relocate.c
+++ b/src/drivers/intel/fsp1_1/fsp_relocate.c
@@ -19,11 +19,10 @@
#include <console/console.h>
#include <cbmem.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
#include <stdlib.h>
#include <stdint.h>
#include <string.h>
-#include <uefi_types.h>
#define FSP_DBG_LVL BIOS_NEVER
diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c
index e6e3889eb4..d44f0f0157 100644
--- a/src/drivers/intel/fsp1_1/fsp_util.c
+++ b/src/drivers/intel/fsp1_1/fsp_util.c
@@ -21,7 +21,7 @@
#include <bootstate.h>
#include <cbmem.h>
#include <console/console.h>
-#include "fsp_util.h"
+#include <fsp/util.h>
#include <timestamp.h>
/* Locate the FSP binary in the coreboot filesystem */
diff --git a/src/drivers/intel/fsp1_1/hob.c b/src/drivers/intel/fsp1_1/hob.c
index 05044cb778..467d4afd0f 100644
--- a/src/drivers/intel/fsp1_1/hob.c
+++ b/src/drivers/intel/fsp1_1/hob.c
@@ -23,7 +23,7 @@
#include <bootstate.h>
#include <cbmem.h>
#include <console/console.h>
-#include "fsp_util.h"
+#include <fsp/util.h>
#include <ip_checksum.h>
#include <lib.h> // hexdump
#include <string.h>
diff --git a/src/drivers/intel/fsp1_1/include/fsp/api.h b/src/drivers/intel/fsp1_1/include/fsp/api.h
new file mode 100644
index 0000000000..414532c09b
--- /dev/null
+++ b/src/drivers/intel/fsp1_1/include/fsp/api.h
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _FSP1_1_API_H_
+#define _FSP1_1_API_H_
+
+#define FSP_SIG 0x48505346 /* 'FSPH' */
+
+/* All the FSP headers need to have UEFI types provided before inclusion. */
+#include <fsp/uefi_binding.h>
+
+/*
+ * Intel's code does not have a handle on changing global packing state.
+ * Therefore, one needs to protect against packing policies that are set
+ * globally for a compliation unit just by including a header file.
+ */
+#pragma pack(push)
+
+#include <vendorcode/intel/fsp/fsp1_1/IntelFspPkg/Include/FspApi.h>
+#include <vendorcode/intel/fsp/fsp1_1/IntelFspPkg/Include/FspInfoHeader.h>
+
+/* Restore original packing policy. */
+#pragma pack(pop)
+
+#endif
diff --git a/src/drivers/intel/fsp1_1/fsp_gop.h b/src/drivers/intel/fsp1_1/include/fsp/gop.h
index 2999369e2f..14bada6f96 100644
--- a/src/drivers/intel/fsp1_1/fsp_gop.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/gop.h
@@ -17,8 +17,8 @@
* Foundation, Inc.
*/
-#ifndef _FSP_GOP_H_
-#define _FSP_GOP_H_
+#ifndef _FSP1_1_GOP_H_
+#define _FSP1_1_GOP_H_
/* GOP support */
#if IS_ENABLED(CONFIG_GOP_SUPPORT)
diff --git a/src/drivers/intel/fsp1_1/include/fsp/soc_binding.h b/src/drivers/intel/fsp1_1/include/fsp/soc_binding.h
new file mode 100644
index 0000000000..1625040be8
--- /dev/null
+++ b/src/drivers/intel/fsp1_1/include/fsp/soc_binding.h
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _FSP1_1_SOC_BINDING_H_
+#define _FSP1_1_SOC_BINDING_H_
+
+/* All the FSP headers need to have UEFI types provided before inclusion. */
+#include <fsp/uefi_binding.h>
+
+/*
+ * Intel's code does not have a handle on changing global packing state.
+ * Therefore, one needs to protect against packing policies that are set
+ * globally for a compliation unit just by including a header file.
+ */
+#pragma pack(push)
+
+/*
+ * This file is found by way of the Kconfig FSP_INCLUDE_PATH option. It is
+ * a per implementation specific header. i.e. different FSP implementations
+ * for different chipsets.
+ */
+#include <FspUpdVpd.h>
+
+/* Restore original packing policy. */
+#pragma pack(pop)
+
+#endif
diff --git a/src/drivers/intel/fsp1_1/include/fsp/uefi_binding.h b/src/drivers/intel/fsp1_1/include/fsp/uefi_binding.h
new file mode 100644
index 0000000000..73a8a4a7dc
--- /dev/null
+++ b/src/drivers/intel/fsp1_1/include/fsp/uefi_binding.h
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _FSP1_1_UEFI_BINDING_H_
+#define _FSP1_1_UEFI_BINDING_H_
+
+/*
+ * Intel's code does not have a handle on changing global packing state.
+ * Therefore, one needs to protect against packing policies that are set
+ * globally for a compliation unit just by including a header file.
+ */
+#pragma pack(push)
+
+/*
+ * Pull in the UEFI types from 2.4. Smarter decisions can be made on what
+ * version to bind to, but for now 2.4 is standard for FSP 1.1.
+ */
+#include <vendorcode/intel/edk2/uefi_2.4/uefi_types.h>
+
+/* Restore original packing policy. */
+#pragma pack(pop)
+
+#endif
diff --git a/src/drivers/intel/fsp1_1/fsp_util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h
index 51ecb98f2c..9695b3b697 100644
--- a/src/drivers/intel/fsp1_1/fsp_util.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/util.h
@@ -18,29 +18,16 @@
* Foundation, Inc.
*/
-#ifndef FSP_UTIL_H
-#define FSP_UTIL_H
+#ifndef FSP1_1_UTIL_H
+#define FSP1_1_UTIL_H
-#include <types.h>
-#include <arch/cpu.h>
-#include <fsp_gop.h>
+#include <fsp/api.h>
+/* Current users expect to get the SoC's FSP definitions by including util.h. */
+#include <fsp/soc_binding.h>
+#include <fsp/gop.h>
#include <program_loading.h>
#include <region.h>
-/*
- * The following are functions with prototypes defined in the EDK2 headers. The
- * EDK2 headers are included with chipset_fsp_util.h. Define the following
- * names to reduce the use of CamelCase in the other source files.
- */
-#define GetHobList get_hob_list
-#define GetNextHob get_next_hob
-#define GetFirstHob get_first_hob
-#define GetNextGuidHob get_next_guid_hob
-#define GetFirstGuidHob get_first_guid_hob
-
-/* Include the EDK2 headers */
-#include <soc/chipset_fsp_util.h>
-
/* find_fsp() should only be called from assembly code. */
FSP_INFO_HEADER *find_fsp(uintptr_t fsp_base_address);
/* Set FSP's runtime information. */
@@ -88,8 +75,6 @@ int fsp_relocate(struct prog *fsp_relocd, const struct region_device *fsp_src);
#define FSP_IMAGE_ATTRIBUTE_LOC 32
#define GRAPHICS_SUPPORT_BIT (1 << 0)
-#define FSP_SIG 0x48505346 /* 'FSPH' */
-
#define ERROR_NO_FV_SIG 1
#define ERROR_NO_FFS_GUID 2
#define ERROR_NO_INFO_HEADER 3
@@ -101,4 +86,11 @@ int fsp_relocate(struct prog *fsp_relocd, const struct region_device *fsp_src);
extern void *FspHobListPtr;
#endif
-#endif /* FSP_UTIL_H */
+/* TODO: Remove the EFI types and decorations from coreboot implementations. */
+VOID * EFIAPI get_hob_list(VOID);
+VOID * EFIAPI get_next_hob(UINT16 type, CONST VOID *hob_start);
+VOID * EFIAPI get_first_hob(UINT16 type);
+VOID * EFIAPI get_next_guid_hob(CONST EFI_GUID * guid, CONST VOID *hob_start);
+VOID * EFIAPI get_first_guid_hob(CONST EFI_GUID * guid);
+
+#endif /* FSP1_1_UTIL_H */
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index 755c15a0cf..fae97b8219 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -51,19 +51,11 @@ smm-y += smihandler.c
smm-y += spi.c
smm-y += tsc_freq.c
-CPPFLAGS_common += -I$(src)/arch/x86/include/
CPPFLAGS_common += -I$(src)/soc/intel/braswell/
CPPFLAGS_common += -I$(src)/soc/intel/braswell/include
CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)
-CPPFLAGS_common += -I$(src)/drivers/intel/fsp1_1
-CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1
-CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4
-CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include
-CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Ia32
-CPPFLAGS_common += -I$(CONFIG_FSP_INCLUDE_PATH)
-
# Run an intermediate step when producing coreboot.rom
# that adds additional components to the final firmware
# image outside of CBFS
diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c
index e1065e22d1..b8be3c6fec 100644
--- a/src/soc/intel/braswell/acpi.c
+++ b/src/soc/intel/braswell/acpi.c
@@ -35,7 +35,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <ec/google/chromeec/ec.h>
-#include <fsp_gop.h>
+#include <fsp/gop.h>
#include <rules.h>
#include <soc/acpi.h>
#include <soc/gfx.h>
diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c
index c986507968..6f227407de 100644
--- a/src/soc/intel/braswell/chip.c
+++ b/src/soc/intel/braswell/chip.c
@@ -22,7 +22,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h
index 191fc01926..ff68014d9c 100644
--- a/src/soc/intel/braswell/chip.h
+++ b/src/soc/intel/braswell/chip.h
@@ -27,7 +27,7 @@
#define _SOC_CHIP_H_
#include <stdint.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
#include <soc/pci_devs.h>
#define SVID_CONFIG1 1
diff --git a/src/soc/intel/braswell/include/soc/chipset_fsp_util.h b/src/soc/intel/braswell/include/soc/chipset_fsp_util.h
deleted file mode 100644
index c269a613aa..0000000000
--- a/src/soc/intel/braswell/include/soc/chipset_fsp_util.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Intel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef CHIPSET_FSP_UTIL_H
-#define CHIPSET_FSP_UTIL_H
-
-/*
- * Include the FSP binary interface files
- *
- * These files include the necessary UEFI constants and data structures
- * that are used to interface to the FSP binary.
- */
-
-#include <uefi_types.h> /* UEFI data types */
-#include <IntelFspPkg/Include/FspApi.h> /* FSP API definitions */
-#include <IntelFspPkg/Include/FspInfoHeader.h> /* FSP binary layout */
-#include <MdePkg/Include/Pi/PiBootMode.h> /* UEFI boot mode definitions */
-#include <MdePkg/Include/Pi/PiFirmwareFile.h> /* UEFI file definitions */
-#include <MdePkg/Include/Pi/PiFirmwareVolume.h> /* UEFI file system defs */
-#include <MdePkg/Include/Uefi/UefiMultiPhase.h> /* UEFI memory types */
-#include <MdePkg/Include/Pi/PiHob.h> /* Hand off block definitions */
-#include <MdePkg/Include/Library/HobLib.h> /* HOB routine declarations */
-#include <FspUpdVpd.h> /* Vital/updatable product data definitions */
-
-#endif /* CHIPSET_FSP_UTIL_H */
diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h
index 770a39d115..a735c04db5 100644
--- a/src/soc/intel/braswell/include/soc/romstage.h
+++ b/src/soc/intel/braswell/include/soc/romstage.h
@@ -23,7 +23,7 @@
#include <stdint.h>
#include <arch/cpu.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
#include <soc/pei_data.h>
#include <soc/pm.h>
#include <soc/intel/common/romstage.h>
diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c
index 7821a2a1ca..390e050ab8 100644
--- a/src/soc/intel/braswell/northcluster.c
+++ b/src/soc/intel/braswell/northcluster.c
@@ -25,7 +25,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
#include <soc/intel/common/memmap.h>
#include <soc/iomap.h>
#include <soc/iosf.h>
diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c
index 3e1e02fb19..26c23bc486 100644
--- a/src/soc/intel/braswell/ramstage.c
+++ b/src/soc/intel/braswell/ramstage.c
@@ -29,7 +29,7 @@
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
#include <romstage_handoff.h>
#include <soc/gpio.h>
#include <soc/lpc.h>
diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c
index 1dbff5478e..2286cd48e7 100644
--- a/src/soc/intel/braswell/romstage/romstage.c
+++ b/src/soc/intel/braswell/romstage/romstage.c
@@ -40,7 +40,7 @@
#include <timestamp.h>
#include <reset.h>
#include <vendorcode/google/chromeos/chromeos.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
#include <soc/intel/common/mrc_cache.h>
#include <soc/gpio.h>
#include <soc/iomap.h>
diff --git a/src/soc/intel/common/fsp_ramstage.c b/src/soc/intel/common/fsp_ramstage.c
index 41c0b1c312..d1f2e49aff 100644
--- a/src/soc/intel/common/fsp_ramstage.c
+++ b/src/soc/intel/common/fsp_ramstage.c
@@ -22,7 +22,7 @@
#include <cbmem.h>
#include <cbfs.h>
#include <console/console.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
#include <lib.h>
#include <soc/intel/common/memmap.h>
#include <soc/intel/common/ramstage.h>
diff --git a/src/soc/intel/common/raminit.c b/src/soc/intel/common/raminit.c
index ddf567591d..bdb23e2b64 100644
--- a/src/soc/intel/common/raminit.c
+++ b/src/soc/intel/common/raminit.c
@@ -19,7 +19,7 @@
#include <cbmem.h>
#include <console/console.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
#include <lib.h> /* hexdump */
#include <reset.h>
#include <soc/intel/common/memmap.h>
diff --git a/src/soc/intel/common/ramstage.h b/src/soc/intel/common/ramstage.h
index 414142a8ae..d6cb895174 100644
--- a/src/soc/intel/common/ramstage.h
+++ b/src/soc/intel/common/ramstage.h
@@ -21,7 +21,7 @@
#ifndef _INTEL_COMMON_RAMSTAGE_H_
#define _INTEL_COMMON_RAMSTAGE_H_
-#include <fsp_util.h>
+#include <fsp/util.h>
#include <soc/intel/common/util.h>
#include <stdint.h>
diff --git a/src/soc/intel/common/romstage.h b/src/soc/intel/common/romstage.h
index 440cad75f5..b35ff6652a 100644
--- a/src/soc/intel/common/romstage.h
+++ b/src/soc/intel/common/romstage.h
@@ -24,7 +24,7 @@
#include <stdint.h>
#include <arch/cpu.h>
#include <memory_info.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
#include <soc/intel/common/util.h>
#include <soc/pei_data.h>
#include <soc/pm.h> /* chip_power_state */
diff --git a/src/soc/intel/common/vbt.c b/src/soc/intel/common/vbt.c
index 0e46b70977..b12ec04712 100644
--- a/src/soc/intel/common/vbt.c
+++ b/src/soc/intel/common/vbt.c
@@ -20,7 +20,7 @@
#include <cbfs.h>
#include <console/console.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
#include <lib.h>
#include <soc/intel/common/ramstage.h>
#include <string.h>
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index 32ecb5d60b..38668da4b1 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -61,19 +61,12 @@ smm-$(CONFIG_SPI_FLASH_SMM) += flash_controller.c
smm-y += tsc_freq.c
smm-$(CONFIG_UART_DEBUG) += uart_debug.c
-CPPFLAGS_common += -I$(src)/arch/x86/include/
CPPFLAGS_common += -I$(src)/soc/intel/skylake
CPPFLAGS_common += -I$(src)/soc/intel/skylake/include
+# Currently used for microcode path.
CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)
-CPPFLAGS_common += -I$(src)/drivers/intel/fsp1_1
-CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1
-CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4
-CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include
-CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Ia32
-CPPFLAGS_common += -I$(CONFIG_FSP_INCLUDE_PATH)
-
# Run an intermediate step when producing coreboot.rom
# that adds additional components to the final firmware
# image outside of CBFS
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 2c498838b5..afb0ff6b70 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -23,7 +23,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
#include <string.h>
diff --git a/src/soc/intel/skylake/include/soc/chipset_fsp_util.h b/src/soc/intel/skylake/include/soc/chipset_fsp_util.h
deleted file mode 100644
index 2c05f01b79..0000000000
--- a/src/soc/intel/skylake/include/soc/chipset_fsp_util.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Intel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _CHIPSET_FSP_UTIL_H_
-#define _CHIPSET_FSP_UTIL_H_
-
-/*
- * Include the FSP binary interface files
- *
- * These files include the necessary UEFI constants and data structures
- * that are used to interface to the FSP binary.
- */
-
-#include <uefi_types.h> /* UEFI data types */
-#include <IntelFspPkg/Include/FspApi.h> /* FSP API definitions */
-#include <IntelFspPkg/Include/FspInfoHeader.h> /* FSP binary layout */
-#include <MdePkg/Include/Pi/PiBootMode.h> /* UEFI boot mode definitions */
-#include <MdePkg/Include/Pi/PiFirmwareFile.h> /* UEFI file definitions */
-#include <MdePkg/Include/Pi/PiFirmwareVolume.h> /* UEFI file system defs */
-#include <MdePkg/Include/Uefi/UefiMultiPhase.h> /* UEFI memory types */
-#include <MdePkg/Include/Pi/PiHob.h> /* Hand off block definitions */
-#include <MdePkg/Include/Library/HobLib.h> /* HOB routine declarations */
-#include <FspUpdVpd.h> /* Vital/updatable product data definitions */
-
-#endif /* _CHIPSET_FSP_UTIL_H_ */
diff --git a/src/soc/intel/skylake/ramstage.c b/src/soc/intel/skylake/ramstage.c
index 51e9b31d65..3646843e87 100644
--- a/src/soc/intel/skylake/ramstage.c
+++ b/src/soc/intel/skylake/ramstage.c
@@ -18,9 +18,6 @@
* Foundation, Inc.
*/
-#include <bootstate.h>
-#include <console/console.h>
-#include <fsp_util.h>
#include <soc/ramstage.h>
#include <soc/intel/common/ramstage.h>
diff --git a/src/vendorcode/intel/Kconfig b/src/vendorcode/intel/Kconfig
index 0da26f0fbd..754c48716c 100644
--- a/src/vendorcode/intel/Kconfig
+++ b/src/vendorcode/intel/Kconfig
@@ -22,3 +22,6 @@ config FSP_VENDORCODE_HEADER_PATH
default "fsp1_0/ivybridge_bd82x6x" if CPU_INTEL_FSP_MODEL_306AX && SOUTHBRIDGE_INTEL_FSP_BD82X6X
default "fsp1_0/baytrail" if SOC_INTEL_FSP_BAYTRAIL
default "fsp1_0/rangeley" if CPU_INTEL_FSP_MODEL_406DX
+
+config UEFI_2_4_BINDING
+ def_bool n
diff --git a/src/vendorcode/intel/Makefile.inc b/src/vendorcode/intel/Makefile.inc
index 2cb486b599..b95d4f9c76 100644
--- a/src/vendorcode/intel/Makefile.inc
+++ b/src/vendorcode/intel/Makefile.inc
@@ -25,3 +25,13 @@ ramstage-y += $(FSP_C_INPUTS)
CFLAGS_x86_32 += -Isrc/vendorcode/intel/$(FSP_PATH)/include
endif
+
+ifeq ($(CONFIG_UEFI_2_4_BINDING),y)
+# ProccessorBind.h provided in Ia32 directory. Types are derived from ia32.
+# It's possible to provide our own ProcessorBind.h using posix types. However,
+# ProcessorBind.h isn't just about types. There's compiler definitions as well
+# as ABI enforcement. Luckily long is not used in Ia32/ProcessorBind.h for
+# a fixed width type.
+CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Ia32
+CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include
+endif
diff --git a/src/vendorcode/intel/edk2/uefi_2.4/uefi_types.h b/src/vendorcode/intel/edk2/uefi_2.4/uefi_types.h
index e17361ed0c..e68f8c9fb0 100644
--- a/src/vendorcode/intel/edk2/uefi_2.4/uefi_types.h
+++ b/src/vendorcode/intel/edk2/uefi_2.4/uefi_types.h
@@ -37,15 +37,15 @@ are permitted provided that the following conditions are met:
#define __APPLE__ 0
#include <stdlib.h>
#include <Uefi/UefiBaseType.h>
-#include <MdePkg/Include/Pi/PiBootMode.h>
-#include <MdePkg/Include/Pi/PiFirmwareFile.h>
-#include <MdePkg/Include/Pi/PiFirmwareVolume.h>
-#include <MdePkg/Include/Uefi/UefiMultiPhase.h>
-#include <MdePkg/Include/Pi/PiHob.h>
-#include <MdePkg/Include/Protocol/GraphicsOutput.h>
-#include <MdePkg/Include/Library/HobLib.h>
-#include <MdePkg/Include/Guid/FirmwareFileSystem2.h>
-#include <MdePkg/Include/IndustryStandard/PeImage.h>
+#include <Pi/PiBootMode.h>
+#include <Pi/PiFirmwareFile.h>
+#include <Pi/PiFirmwareVolume.h>
+#include <Uefi/UefiMultiPhase.h>
+#include <Pi/PiHob.h>
+#include <Protocol/GraphicsOutput.h>
+#include <Library/HobLib.h>
+#include <Guid/FirmwareFileSystem2.h>
+#include <IndustryStandard/PeImage.h>
///
/// For GNU assembly code, .global or .globl can declare global symbols.