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-rw-r--r--src/soc/intel/cannonlake/chip.c9
-rw-r--r--src/soc/intel/cannonlake/include/soc/itss.h3
2 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index 6a3324b7fd..0529c5ca8c 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -21,9 +21,11 @@
#include <fsp/util.h>
#include <intelblocks/acpi.h>
#include <intelblocks/chip.h>
+#include <intelblocks/itss.h>
#include <intelblocks/xdci.h>
#include <romstage_handoff.h>
#include <soc/intel/common/vbt.h>
+#include <soc/itss.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
#include <string.h>
@@ -96,11 +98,18 @@ const char *soc_acpi_name(const struct device *dev)
void soc_init_pre_device(void *chip_info)
{
+ /* Snapshot the current GPIO IRQ polarities. FSP is setting a
+ * default policy that doesn't honor boards' requirements. */
+ itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
+
/* Perform silicon specific init. */
fsp_silicon_init(romstage_handoff_is_resume());
/* Display FIRMWARE_VERSION_INFO_HOB */
fsp_display_fvi_version_hob();
+
+ /* Restore GPIO IRQ polarities back to previous settings. */
+ itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
}
static void pci_domain_set_resources(struct device *dev)
diff --git a/src/soc/intel/cannonlake/include/soc/itss.h b/src/soc/intel/cannonlake/include/soc/itss.h
index 06dcc2e8d5..0d8b2ca3c0 100644
--- a/src/soc/intel/cannonlake/include/soc/itss.h
+++ b/src/soc/intel/cannonlake/include/soc/itss.h
@@ -16,6 +16,9 @@
#ifndef SOC_INTEL_CNL_ITSS_H
#define SOC_INTEL_CNL_ITSS_H
+#define GPIO_IRQ_START 50
+#define GPIO_IRQ_END ITSS_MAX_IRQ
+
#define ITSS_MAX_IRQ 119
#define IRQS_PER_IPC 32
#define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC)