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-rw-r--r--src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb2
-rw-r--r--src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb2
-rw-r--r--src/mainboard/google/zork/variants/baseboard/ramstage_common.c2
-rw-r--r--src/soc/amd/picasso/acp.c2
-rw-r--r--src/soc/amd/picasso/chip.h2
5 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
index 42219d7a16..a0f6636b7f 100644
--- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
+++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
@@ -8,7 +8,7 @@ chip soc/amd/picasso
register "acp_pin_cfg" = "I2S_PINS_I2S_TDM"
register "acp_i2s_wake_enable" = "0"
- register "acpi_pme_enable" = "0"
+ register "acp_pme_enable" = "0"
# Start : OPN Performance Configuration
# (Configuratin that is common for all variants)
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
index 16206439ee..169451931d 100644
--- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
+++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
@@ -8,7 +8,7 @@ chip soc/amd/picasso
register "acp_pin_cfg" = "I2S_PINS_I2S_TDM"
register "acp_i2s_wake_enable" = "0"
- register "acpi_pme_enable" = "0"
+ register "acp_pme_enable" = "0"
# Start : OPN Performance Configuration
# (Configuratin that is common for all variants)
diff --git a/src/mainboard/google/zork/variants/baseboard/ramstage_common.c b/src/mainboard/google/zork/variants/baseboard/ramstage_common.c
index 664f659602..c2a0294bbc 100644
--- a/src/mainboard/google/zork/variants/baseboard/ramstage_common.c
+++ b/src/mainboard/google/zork/variants/baseboard/ramstage_common.c
@@ -71,7 +71,7 @@ static void update_hp_int_odl(void)
*/
soc_cfg = config_of_soc();
soc_cfg->acp_i2s_wake_enable = 1;
- soc_cfg->acpi_pme_enable = 1;
+ soc_cfg->acp_pme_enable = 1;
}
static void update_dmic_gpio(void)
diff --git a/src/soc/amd/picasso/acp.c b/src/soc/amd/picasso/acp.c
index 8e6f4cfbbb..9ee29551d4 100644
--- a/src/soc/amd/picasso/acp.c
+++ b/src/soc/amd/picasso/acp.c
@@ -45,7 +45,7 @@ static void init(struct device *dev)
/* Enable ACP_PME_EN and ACP_I2S_WAKE_EN for I2S_WAKE event */
acp_update32(bar, ACP_I2S_WAKE_EN, WAKE_EN_MASK, !!cfg->acp_i2s_wake_enable);
- acp_update32(bar, ACP_PME_EN, PME_EN_MASK, !!cfg->acpi_pme_enable);
+ acp_update32(bar, ACP_PME_EN, PME_EN_MASK, !!cfg->acp_pme_enable);
if (cfg->acp_pin_cfg == I2S_PINS_I2S_TDM)
sb_clk_output_48Mhz(); /* Internal connection to I2S */
diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h
index ac1a12c6b1..ad492e0353 100644
--- a/src/soc/amd/picasso/chip.h
+++ b/src/soc/amd/picasso/chip.h
@@ -63,7 +63,7 @@ struct soc_amd_picasso_config {
/* Enable ACP I2S wake feature (0 = disable, 1 = enable) */
u8 acp_i2s_wake_enable;
/* Enable ACP PME (0 = disable, 1 = enable) */
- u8 acpi_pme_enable;
+ u8 acp_pme_enable;
/**
* IRQ 0 - 15 have a default trigger of edge and default polarity of high.