summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/cpu/amd/agesa/family12/fixme.c3
-rw-r--r--src/cpu/amd/agesa/family14/fixme.c3
-rw-r--r--src/cpu/amd/agesa/family15tn/fixme.c3
-rw-r--r--src/cpu/amd/agesa/family16kb/fixme.c3
-rw-r--r--src/cpu/amd/family_10h-family_15h/model_10xxx_init.c2
-rw-r--r--src/cpu/amd/pi/00630F01/fixme.c3
-rw-r--r--src/cpu/amd/pi/00660F01/fixme.c3
-rw-r--r--src/cpu/amd/pi/00730F01/fixme.c3
-rw-r--r--src/drivers/amd/agesa/s3_mtrr.c4
-rw-r--r--src/include/cpu/amd/mtrr.h12
-rw-r--r--src/northbridge/amd/amdmct/mct/mct_d.c4
-rw-r--r--src/northbridge/amd/amdmct/mct/mctdqs_d.c2
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mct_d.c6
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c2
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/s3utils.c37
-rw-r--r--src/southbridge/amd/rs780/gfx.c5
-rw-r--r--src/southbridge/amd/sr5650/sr5650.c4
17 files changed, 62 insertions, 37 deletions
diff --git a/src/cpu/amd/agesa/family12/fixme.c b/src/cpu/amd/agesa/family12/fixme.c
index e97a819fda..9df43e5f61 100644
--- a/src/cpu/amd/agesa/family12/fixme.c
+++ b/src/cpu/amd/agesa/family12/fixme.c
@@ -15,6 +15,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
+#include <cpu/amd/mtrr.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <AGESA.h>
#include "amdlib.h"
@@ -40,7 +41,7 @@ void amd_initcpuio(void)
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
PciData = 0x00DFFF00;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader);
+ LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
PciData = (UINT32) MsrReg;
diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c
index 978c25ff6f..a49cefbaa3 100644
--- a/src/cpu/amd/agesa/family14/fixme.c
+++ b/src/cpu/amd/agesa/family14/fixme.c
@@ -15,6 +15,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
+#include <cpu/amd/mtrr.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <AGESA.h>
#include "amdlib.h"
@@ -51,7 +52,7 @@ void amd_initcpuio(void)
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
PciData = 0x00FECF00; // last address before non-posted range
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader);
+ LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
PciData = (UINT32) MsrReg;
diff --git a/src/cpu/amd/agesa/family15tn/fixme.c b/src/cpu/amd/agesa/family15tn/fixme.c
index 7e493f9dda..a0ae193bcf 100644
--- a/src/cpu/amd/agesa/family15tn/fixme.c
+++ b/src/cpu/amd/agesa/family15tn/fixme.c
@@ -15,6 +15,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
+#include <cpu/amd/mtrr.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <AGESA.h>
#include "amdlib.h"
@@ -47,7 +48,7 @@ void amd_initcpuio(void)
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
PciData = 0x00FECF00; /* last address before non-posted range */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
+ LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
PciData = (UINT32)MsrReg;
diff --git a/src/cpu/amd/agesa/family16kb/fixme.c b/src/cpu/amd/agesa/family16kb/fixme.c
index c761d6d22f..2d74c7b769 100644
--- a/src/cpu/amd/agesa/family16kb/fixme.c
+++ b/src/cpu/amd/agesa/family16kb/fixme.c
@@ -15,6 +15,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
+#include <cpu/amd/mtrr.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <AGESA.h>
#include "amdlib.h"
@@ -47,7 +48,7 @@ void amd_initcpuio(void)
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
PciData = 0x00FECF00; /* last address before non-posted range */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
+ LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
PciData = (UINT32)MsrReg;
diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
index 2374503287..c0316e5dd7 100644
--- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
+++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
@@ -90,7 +90,7 @@ static void model_10xxx_init(struct device *dev)
disable_cache();
for (i = 0x2; i < 0x10; i++) {
- wrmsr(0x00000200 | i, msr);
+ wrmsr(MTRR_PHYS_BASE(0) | i, msr);
}
enable_cache();
diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c
index 11cab62ba8..ae2a2dfe88 100644
--- a/src/cpu/amd/pi/00630F01/fixme.c
+++ b/src/cpu/amd/pi/00630F01/fixme.c
@@ -15,6 +15,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
+#include <cpu/amd/mtrr.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <Porting.h>
#include <AGESA.h>
@@ -52,7 +53,7 @@ void amd_initcpuio(void)
/* last address before non-posted range */
PciData = 0x00FECF00;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader);
+ LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
PciData = (UINT32)MsrReg;
diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c
index ee8728d34d..e028b6f85b 100644
--- a/src/cpu/amd/pi/00660F01/fixme.c
+++ b/src/cpu/amd/pi/00660F01/fixme.c
@@ -15,6 +15,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
+#include <cpu/amd/mtrr.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <Porting.h>
#include <AGESA.h>
@@ -51,7 +52,7 @@ void amd_initcpuio(void)
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
PciData = 0x00FECF00; /* last address before non-posted range */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader);
+ LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
PciData = (UINT32)MsrReg;
diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c
index 4350572b9b..163066b6d8 100644
--- a/src/cpu/amd/pi/00730F01/fixme.c
+++ b/src/cpu/amd/pi/00730F01/fixme.c
@@ -15,6 +15,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
+#include <cpu/amd/mtrr.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <Porting.h>
#include <AGESA.h>
@@ -51,7 +52,7 @@ void amd_initcpuio(void)
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
PciData = 0x00FECF00; /* last address before non-posted range */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader);
+ LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
PciData = (UINT32)MsrReg;
diff --git a/src/drivers/amd/agesa/s3_mtrr.c b/src/drivers/amd/agesa/s3_mtrr.c
index 531ad4565b..4df7b05bac 100644
--- a/src/drivers/amd/agesa/s3_mtrr.c
+++ b/src/drivers/amd/agesa/s3_mtrr.c
@@ -61,9 +61,9 @@ void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size)
/* SYSCFG_MSR */
write_mtrr(&nvram_pos, SYSCFG_MSR);
/* TOM */
- write_mtrr(&nvram_pos, 0xC001001A);
+ write_mtrr(&nvram_pos, TOP_MEM);
/* TOM2 */
- write_mtrr(&nvram_pos, 0xC001001D);
+ write_mtrr(&nvram_pos, TOP_MEM2);
*mtrr_store_size = nvram_pos - (u8*) mtrr_store;
}
diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h
index 33b5939e2f..46d66f8cef 100644
--- a/src/include/cpu/amd/mtrr.h
+++ b/src/include/cpu/amd/mtrr.h
@@ -1,6 +1,18 @@
#ifndef CPU_AMD_MTRR_H
#define CPU_AMD_MTRR_H
+/* FIXME
+ * Replace
+ * #define IORR_FIRST 0xC0010016
+ * #define IORR_LAST 0xC0010019
+ * with
+ * #define IORR0_BASE 0xC0010016
+ * #define IORR0_MASK 0xC0010017
+ * #define IORR1_BASE 0xC0010018
+ * #define IORR1_MASK 0xC0010019
+ * those are also defined in vendorcode <AGESA.h> file.
+ */
+
#define IORR_FIRST 0xC0010016
#define IORR_LAST 0xC0010019
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c
index 91103ffb4f..d03ae9ca98 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct/mct_d.c
@@ -3255,7 +3255,7 @@ static void mct_init(struct MCTStatStruc *pMCTstat,
pDCTstat->DRPresent = 1;
/* enable extend PCI configuration access */
- addr = 0xC001001F;
+ addr = NB_CFG_MSR;
_RDMSR(addr, &lo, &hi);
if (hi & (1 << (46-32))) {
pDCTstat->Status |= 1 << SB_ExtConfig;
@@ -3556,7 +3556,7 @@ static u8 CheckNBCOFEarlyArbEn(struct MCTStatStruc *pMCTstat,
*/
/* 3*(Fn2xD4[NBFid]+4)/(2^NbDid)/(3+Fn2x94[MemClkFreq]) */
- _RDMSR(0xC0010071, &lo, &hi);
+ _RDMSR(MSR_COFVID_STS, &lo, &hi);
if (lo & (1 << 22))
NbDid |= 1;
diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
index 39c11ce7da..5aadcccf56 100644
--- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
@@ -816,7 +816,7 @@ void SetTargetWTIO_D(u32 TestAddr)
u32 lo, hi;
hi = TestAddr >> 24;
lo = TestAddr << 8;
- _WRMSR(0xC0010016, lo, hi); /* IORR0 Base */
+ _WRMSR(IORR_FIRST, lo, hi); /* IORR0 Base */
hi = 0xFF;
lo = 0xFC000800; /* 64MB Mask */
_WRMSR(0xC0010017, lo, hi); /* IORR0 Mask */
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index b94c68c931..27aaf1a54e 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -6789,7 +6789,7 @@ static void mct_InitialMCT_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc
boost_states = (Get_NB32(pDCTstat->dev_link, 0x15c) >> 2) & 0x7;
/* Retrieve and store the TSC frequency (P0 COF) */
- p0_state_msr = rdmsr(0xc0010064 + boost_states);
+ p0_state_msr = rdmsr(PSTATE_0_MSR + boost_states);
cpu_fid = p0_state_msr.lo & 0x3f;
cpu_did = (p0_state_msr.lo >> 6) & 0x7;
cpu_divisor = (0x1 << cpu_did);
@@ -6833,7 +6833,7 @@ static void mct_init(struct MCTStatStruc *pMCTstat,
pDCTstat->DRPresent = 1;
/* enable extend PCI configuration access */
- addr = 0xC001001F;
+ addr = NB_CFG_MSR;
_RDMSR(addr, &lo, &hi);
if (hi & (1 << (46-32))) {
pDCTstat->Status |= 1 << SB_ExtConfig;
@@ -7333,7 +7333,7 @@ static u8 CheckNBCOFEarlyArbEn(struct MCTStatStruc *pMCTstat,
*/
/* 3*(Fn2xD4[NBFid]+4)/(2^NbDid)/(3+Fn2x94[MemClkFreq]) */
- _RDMSR(0xC0010071, &lo, &hi);
+ _RDMSR(MSR_COFVID_STS, &lo, &hi);
if (lo & (1 << 22))
NbDid |= 1;
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
index ce93472b9d..8b6a8d41bc 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
@@ -2148,7 +2148,7 @@ void SetTargetWTIO_D(u32 TestAddr)
u32 lo, hi;
hi = TestAddr >> 24;
lo = TestAddr << 8;
- _WRMSR(0xC0010016, lo, hi); /* IORR0 Base */
+ _WRMSR(IORR_FIRST, lo, hi); /* IORR0 Base */
hi = 0xFF;
lo = 0xFC000800; /* 64MB Mask */
_WRMSR(0xC0010017, lo, hi); /* IORR0 Mask */
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
index 388f064848..6fd5b364a4 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
@@ -17,6 +17,9 @@
#include <arch/cpu.h>
#include <arch/acpi.h>
#include <cpu/x86/msr.h>
+#include <cpu/amd/msr.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/amd/mtrr.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
@@ -358,17 +361,18 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data *persistent_da
data->f2x1b0 = pci_read_config32(dev_fn2, 0x1b0);
data->f3x44 = pci_read_config32(dev_fn3, 0x44);
for (i = 0; i < 16; i++) {
- data->msr0000020[i] = rdmsr_uint64_t(0x00000200 | i);
+ data->msr0000020[i] =
+ rdmsr_uint64_t(MTRR_PHYS_BASE(0) | i);
}
- data->msr00000250 = rdmsr_uint64_t(0x00000250);
- data->msr00000258 = rdmsr_uint64_t(0x00000258);
+ data->msr00000250 = rdmsr_uint64_t(MTRR_FIX_64K_00000);
+ data->msr00000258 = rdmsr_uint64_t(MTRR_FIX_16K_80000);
for (i = 0; i < 8; i++)
data->msr0000026[i] = rdmsr_uint64_t(0x00000260 | (i + 8));
- data->msr000002ff = rdmsr_uint64_t(0x000002ff);
- data->msrc0010010 = rdmsr_uint64_t(0xc0010010);
- data->msrc001001a = rdmsr_uint64_t(0xc001001a);
- data->msrc001001d = rdmsr_uint64_t(0xc001001d);
- data->msrc001001f = rdmsr_uint64_t(0xc001001f);
+ data->msr000002ff = rdmsr_uint64_t(MTRR_DEF_TYPE_MSR);
+ data->msrc0010010 = rdmsr_uint64_t(SYSCFG_MSR);
+ data->msrc001001a = rdmsr_uint64_t(TOP_MEM);
+ data->msrc001001d = rdmsr_uint64_t(TOP_MEM2);
+ data->msrc001001f = rdmsr_uint64_t(NB_CFG_MSR);
/* Stage 3 */
data->f2x40 = read_config32_dct(dev_fn2, node, channel, 0x40);
@@ -697,10 +701,11 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data *persiste
write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x1b0, data->f2x1b0);
write_config32_dct(PCI_DEV(0, 0x18 + node, 3), node, channel, 0x44, data->f3x44);
for (i = 0; i < 16; i++) {
- wrmsr_uint64_t(0x00000200 | i, data->msr0000020[i]);
+ wrmsr_uint64_t(MTRR_PHYS_BASE(0) | i,
+ data->msr0000020[i]);
}
- wrmsr_uint64_t(0x00000250, data->msr00000250);
- wrmsr_uint64_t(0x00000258, data->msr00000258);
+ wrmsr_uint64_t(MTRR_FIX_64K_00000, data->msr00000250);
+ wrmsr_uint64_t(MTRR_FIX_16K_80000, data->msr00000258);
/* FIXME
* Restoring these MSRs causes a hang on resume due to
* destroying CAR while still executing from CAR!
@@ -708,11 +713,11 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data *persiste
*/
// for (i = 0; i < 8; i++)
// wrmsr_uint64_t(0x00000260 | (i + 8), data->msr0000026[i]);
- wrmsr_uint64_t(0x000002ff, data->msr000002ff);
- wrmsr_uint64_t(0xc0010010, data->msrc0010010);
- wrmsr_uint64_t(0xc001001a, data->msrc001001a);
- wrmsr_uint64_t(0xc001001d, data->msrc001001d);
- wrmsr_uint64_t(0xc001001f, data->msrc001001f);
+ wrmsr_uint64_t(MTRR_DEF_TYPE_MSR, data->msr000002ff);
+ wrmsr_uint64_t(SYSCFG_MSR, data->msrc0010010);
+ wrmsr_uint64_t(TOP_MEM, data->msrc001001a);
+ wrmsr_uint64_t(TOP_MEM2, data->msrc001001d);
+ wrmsr_uint64_t(NB_CFG_MSR, data->msrc001001f);
}
}
diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c
index a765655ce7..b17aebb0cc 100644
--- a/src/southbridge/amd/rs780/gfx.c
+++ b/src/southbridge/amd/rs780/gfx.c
@@ -34,6 +34,7 @@
#include <device/pci_ops.h>
#include <delay.h>
#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
#include "rs780.h"
/* Trust the original resource allocation. Don't do it again. */
@@ -762,11 +763,11 @@ static void rs780_internal_gfx_enable(struct device *dev)
printk(BIOS_DEBUG, "rs780_internal_gfx_enable dev = 0x%p, nb_dev = 0x%p.\n", dev, nb_dev);
/* The system top memory in 780. */
- sysmem = rdmsr(0xc001001a);
+ sysmem = rdmsr(TOP_MEM);
printk(BIOS_DEBUG, "Sysmem TOM = %x_%x\n", sysmem.hi, sysmem.lo);
pci_write_config32(nb_dev, 0x90, sysmem.lo);
- sysmem = rdmsr(0xc001001D);
+ sysmem = rdmsr(TOP_MEM2);
printk(BIOS_DEBUG, "Sysmem TOM2 = %x_%x\n", sysmem.hi, sysmem.lo);
htiu_write_index(nb_dev, 0x31, sysmem.hi);
htiu_write_index(nb_dev, 0x30, sysmem.lo | 1);
diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c
index 1e85c48986..0f8b265781 100644
--- a/src/southbridge/amd/sr5650/sr5650.c
+++ b/src/southbridge/amd/sr5650/sr5650.c
@@ -304,11 +304,11 @@ void sr5650_set_tom(struct device *nb_dev)
msr_t sysmem;
/* The system top memory in SR56X0. */
- sysmem = rdmsr(0xc001001A);
+ sysmem = rdmsr(TOP_MEM);
printk(BIOS_DEBUG, "Sysmem TOM = %x_%x\n", sysmem.hi, sysmem.lo);
pci_write_config32(nb_dev, 0x90, sysmem.lo);
- sysmem = rdmsr(0xc001001D);
+ sysmem = rdmsr(TOP_MEM2);
printk(BIOS_DEBUG, "Sysmem TOM2 = %x_%x\n", sysmem.hi, sysmem.lo);
htiu_write_index(nb_dev, 0x31, sysmem.hi);
htiu_write_index(nb_dev, 0x30, sysmem.lo | 1);
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-29 10:53:57 +0000