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-rw-r--r--src/soc/intel/apollolake/chip.c2
-rw-r--r--src/soc/intel/apollolake/chip.h7
2 files changed, 8 insertions, 1 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 24c7a599e5..31b6b1747f 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -614,7 +614,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
if (!IS_ENABLED(CONFIG_SOC_INTEL_GLK))
silconfig->MonitorMwaitEnable = 0;
- silconfig->SkipMpInit = 1;
+ silconfig->SkipMpInit = !cfg->use_fsp_mp_init;
/* Disable setting of EISS bit in FSP. */
silconfig->SpiEiss = 0;
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index 63ced94cd5..af465df111 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -152,6 +152,13 @@ struct soc_intel_apollolake_config {
* (1) Power
* (2) Power & Performance */
enum pnp_settings pnp_settings;
+
+ /*
+ * Option for mainboard to skip coreboot MP initialization
+ * 0 = Make use of coreboot MP Init
+ * 1 = Make use of FSP MP Init
+ */
+ uint8_t use_fsp_mp_init;
};
typedef struct soc_intel_apollolake_config config_t;