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-rw-r--r--src/arch/x86/exit_car.S10
-rw-r--r--src/include/cpu/x86/cache.h2
2 files changed, 11 insertions, 1 deletions
diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S
index 806dc9c069..dc356b2cf9 100644
--- a/src/arch/x86/exit_car.S
+++ b/src/arch/x86/exit_car.S
@@ -2,6 +2,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cr.h>
+#include <cpu/x86/cache.h>
.section ".module_parameters", "aw", @progbits
/* stack_top indicates the stack to pull MTRR information from. */
@@ -54,7 +55,14 @@ _start:
movl 4(%esp), %eax
movl %eax, _cbmem_top_ptr
#endif
-
+ /* Make sure _cbmem_top_ptr hits dram before invd */
+ movl $1, %eax
+ cpuid
+ btl $CPUID_FEATURE_CLFLUSH_BIT, %edx
+ jz skip_clflush
+ clflush _cbmem_top_ptr
+
+skip_clflush:
/* chipset_teardown_car() is expected to disable cache-as-ram. */
call chipset_teardown_car
diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h
index 01b202eb1a..62341104a4 100644
--- a/src/include/cpu/x86/cache.h
+++ b/src/include/cpu/x86/cache.h
@@ -8,6 +8,8 @@
#define CR0_CacheDisable (CR0_CD)
#define CR0_NoWriteThrough (CR0_NW)
+#define CPUID_FEATURE_CLFLUSH_BIT 19
+
#if !defined(__ASSEMBLER__)
static inline void wbinvd(void)