diff options
Diffstat (limited to 'src')
10 files changed, 70 insertions, 35 deletions
diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-928.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-928.c index d2828da6da..f75e6b5bd5 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-928.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-928.c @@ -465,9 +465,9 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PI_65_DATA */ 0x04060002, /* DENALI_PI_66_DATA */ 0x04010401, /* DENALI_PI_67_DATA */ - 0x01080801, /* DENALI_PI_68_DATA */ - 0x04020201, /* DENALI_PI_69_DATA */ - 0x01080804, /* DENALI_PI_70_DATA */ + 0x00080801, /* DENALI_PI_68_DATA */ + 0x00020001, /* DENALI_PI_69_DATA */ + 0x00080004, /* DENALI_PI_70_DATA */ 0x00000000, /* DENALI_PI_71_DATA */ 0x04040000, /* DENALI_PI_72_DATA */ 0x0c0c0c04, /* DENALI_PI_73_DATA */ diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-2GB-800.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-2GB-800.c index 062df3a418..0255bdf00f 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-2GB-800.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-2GB-800.c @@ -466,9 +466,9 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PI_65_DATA */ 0x03060002, /* DENALI_PI_66_DATA */ 0x03010301, /* DENALI_PI_67_DATA */ - 0x01080801, /* DENALI_PI_68_DATA */ - 0x04020201, /* DENALI_PI_69_DATA */ - 0x01080804, /* DENALI_PI_70_DATA */ + 0x00080801, /* DENALI_PI_68_DATA */ + 0x00020001, /* DENALI_PI_69_DATA */ + 0x00080004, /* DENALI_PI_70_DATA */ 0x00000000, /* DENALI_PI_71_DATA */ 0x03030000, /* DENALI_PI_72_DATA */ 0x0a0a0a03, /* DENALI_PI_73_DATA */ @@ -682,7 +682,7 @@ struct rk3399_sdram_params params = { 0x00b30080, /* DENALI_PHY_77_DATA */ 0x00000003, /* DENALI_PHY_78_DATA */ 0x00000000, /* DENALI_PHY_79_DATA */ - 0x00030000, /* DENALI_PHY_80_DATA */ + 0x00020000, /* DENALI_PHY_80_DATA */ 0x00000200, /* DENALI_PHY_81_DATA */ 0x00000000, /* DENALI_PHY_82_DATA */ 0x51315152, /* DENALI_PHY_83_DATA */ @@ -810,7 +810,7 @@ struct rk3399_sdram_params params = { 0x00b30080, /* DENALI_PHY_205_DATA */ 0x00000003, /* DENALI_PHY_206_DATA */ 0x00000000, /* DENALI_PHY_207_DATA */ - 0x00030000, /* DENALI_PHY_208_DATA */ + 0x00020000, /* DENALI_PHY_208_DATA */ 0x00000200, /* DENALI_PHY_209_DATA */ 0x00000000, /* DENALI_PHY_210_DATA */ 0x51315152, /* DENALI_PHY_211_DATA */ @@ -938,7 +938,7 @@ struct rk3399_sdram_params params = { 0x00b30080, /* DENALI_PHY_333_DATA */ 0x00000003, /* DENALI_PHY_334_DATA */ 0x00000000, /* DENALI_PHY_335_DATA */ - 0x00030000, /* DENALI_PHY_336_DATA */ + 0x00020000, /* DENALI_PHY_336_DATA */ 0x00000200, /* DENALI_PHY_337_DATA */ 0x00000000, /* DENALI_PHY_338_DATA */ 0x51315152, /* DENALI_PHY_339_DATA */ @@ -1066,7 +1066,7 @@ struct rk3399_sdram_params params = { 0x00b30080, /* DENALI_PHY_461_DATA */ 0x00000003, /* DENALI_PHY_462_DATA */ 0x00000000, /* DENALI_PHY_463_DATA */ - 0x00030000, /* DENALI_PHY_464_DATA */ + 0x00020000, /* DENALI_PHY_464_DATA */ 0x00000200, /* DENALI_PHY_465_DATA */ 0x00000000, /* DENALI_PHY_466_DATA */ 0x51315152, /* DENALI_PHY_467_DATA */ diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-2GB-928.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-2GB-928.c index f14200c804..685b30ea71 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-2GB-928.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-2GB-928.c @@ -466,9 +466,9 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PI_65_DATA */ 0x04060002, /* DENALI_PI_66_DATA */ 0x04010401, /* DENALI_PI_67_DATA */ - 0x01080801, /* DENALI_PI_68_DATA */ - 0x04020201, /* DENALI_PI_69_DATA */ - 0x01080804, /* DENALI_PI_70_DATA */ + 0x00080801, /* DENALI_PI_68_DATA */ + 0x00020001, /* DENALI_PI_69_DATA */ + 0x00080004, /* DENALI_PI_70_DATA */ 0x00000000, /* DENALI_PI_71_DATA */ 0x04040000, /* DENALI_PI_72_DATA */ 0x0c0c0c04, /* DENALI_PI_73_DATA */ diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-4GB-800.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-4GB-800.c index 0b00462d6b..3c8333bcb1 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-4GB-800.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-4GB-800.c @@ -466,9 +466,9 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PI_65_DATA */ 0x03060002, /* DENALI_PI_66_DATA */ 0x03010301, /* DENALI_PI_67_DATA */ - 0x01080801, /* DENALI_PI_68_DATA */ - 0x04020201, /* DENALI_PI_69_DATA */ - 0x01080804, /* DENALI_PI_70_DATA */ + 0x00080801, /* DENALI_PI_68_DATA */ + 0x00020001, /* DENALI_PI_69_DATA */ + 0x00080004, /* DENALI_PI_70_DATA */ 0x00000000, /* DENALI_PI_71_DATA */ 0x03030000, /* DENALI_PI_72_DATA */ 0x0a0a0a03, /* DENALI_PI_73_DATA */ @@ -682,7 +682,7 @@ struct rk3399_sdram_params params = { 0x00b30080, /* DENALI_PHY_77_DATA */ 0x00000003, /* DENALI_PHY_78_DATA */ 0x00000000, /* DENALI_PHY_79_DATA */ - 0x00030000, /* DENALI_PHY_80_DATA */ + 0x00020000, /* DENALI_PHY_80_DATA */ 0x00000200, /* DENALI_PHY_81_DATA */ 0x00000000, /* DENALI_PHY_82_DATA */ 0x51315152, /* DENALI_PHY_83_DATA */ @@ -810,7 +810,7 @@ struct rk3399_sdram_params params = { 0x00b30080, /* DENALI_PHY_205_DATA */ 0x00000003, /* DENALI_PHY_206_DATA */ 0x00000000, /* DENALI_PHY_207_DATA */ - 0x00030000, /* DENALI_PHY_208_DATA */ + 0x00020000, /* DENALI_PHY_208_DATA */ 0x00000200, /* DENALI_PHY_209_DATA */ 0x00000000, /* DENALI_PHY_210_DATA */ 0x51315152, /* DENALI_PHY_211_DATA */ @@ -938,7 +938,7 @@ struct rk3399_sdram_params params = { 0x00b30080, /* DENALI_PHY_333_DATA */ 0x00000003, /* DENALI_PHY_334_DATA */ 0x00000000, /* DENALI_PHY_335_DATA */ - 0x00030000, /* DENALI_PHY_336_DATA */ + 0x00020000, /* DENALI_PHY_336_DATA */ 0x00000200, /* DENALI_PHY_337_DATA */ 0x00000000, /* DENALI_PHY_338_DATA */ 0x51315152, /* DENALI_PHY_339_DATA */ @@ -1066,7 +1066,7 @@ struct rk3399_sdram_params params = { 0x00b30080, /* DENALI_PHY_461_DATA */ 0x00000003, /* DENALI_PHY_462_DATA */ 0x00000000, /* DENALI_PHY_463_DATA */ - 0x00030000, /* DENALI_PHY_464_DATA */ + 0x00020000, /* DENALI_PHY_464_DATA */ 0x00000200, /* DENALI_PHY_465_DATA */ 0x00000000, /* DENALI_PHY_466_DATA */ 0x51315152, /* DENALI_PHY_467_DATA */ diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-4GB-928.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-4GB-928.c index dc7efd9c41..7826d414a7 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-4GB-928.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-4GB-928.c @@ -466,9 +466,9 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PI_65_DATA */ 0x04060002, /* DENALI_PI_66_DATA */ 0x04010401, /* DENALI_PI_67_DATA */ - 0x01080801, /* DENALI_PI_68_DATA */ - 0x04020201, /* DENALI_PI_69_DATA */ - 0x01080804, /* DENALI_PI_70_DATA */ + 0x00080801, /* DENALI_PI_68_DATA */ + 0x00020001, /* DENALI_PI_69_DATA */ + 0x00080004, /* DENALI_PI_70_DATA */ 0x00000000, /* DENALI_PI_71_DATA */ 0x04040000, /* DENALI_PI_72_DATA */ 0x0c0c0c04, /* DENALI_PI_73_DATA */ diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-2GB-24EB-800.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-2GB-24EB-800.c index ac995a82e2..eb0854d59e 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-2GB-24EB-800.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-2GB-24EB-800.c @@ -465,9 +465,9 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PI_65_DATA */ 0x03060002, /* DENALI_PI_66_DATA */ 0x03010301, /* DENALI_PI_67_DATA */ - 0x01080801, /* DENALI_PI_68_DATA */ - 0x04020201, /* DENALI_PI_69_DATA */ - 0x01080804, /* DENALI_PI_70_DATA */ + 0x00080801, /* DENALI_PI_68_DATA */ + 0x00020001, /* DENALI_PI_69_DATA */ + 0x00080004, /* DENALI_PI_70_DATA */ 0x00000000, /* DENALI_PI_71_DATA */ 0x03030000, /* DENALI_PI_72_DATA */ 0x0a0a0a03, /* DENALI_PI_73_DATA */ diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-2GB-24EB-928.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-2GB-24EB-928.c index 62c3392dcd..03e386d48f 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-2GB-24EB-928.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-2GB-24EB-928.c @@ -466,9 +466,9 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PI_65_DATA */ 0x04060002, /* DENALI_PI_66_DATA */ 0x04010401, /* DENALI_PI_67_DATA */ - 0x01080801, /* DENALI_PI_68_DATA */ - 0x04020201, /* DENALI_PI_69_DATA */ - 0x01080804, /* DENALI_PI_70_DATA */ + 0x00080801, /* DENALI_PI_68_DATA */ + 0x00020001, /* DENALI_PI_69_DATA */ + 0x00080004, /* DENALI_PI_70_DATA */ 0x00000000, /* DENALI_PI_71_DATA */ 0x04040000, /* DENALI_PI_72_DATA */ 0x0c0c0c04, /* DENALI_PI_73_DATA */ diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-4GB-04EB-800.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-4GB-04EB-800.c index b4eb49484f..aef335ee8d 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-4GB-04EB-800.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-4GB-04EB-800.c @@ -466,9 +466,9 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PI_65_DATA */ 0x03060002, /* DENALI_PI_66_DATA */ 0x03010301, /* DENALI_PI_67_DATA */ - 0x01080801, /* DENALI_PI_68_DATA */ - 0x04020201, /* DENALI_PI_69_DATA */ - 0x01080804, /* DENALI_PI_70_DATA */ + 0x00080801, /* DENALI_PI_68_DATA */ + 0x00020001, /* DENALI_PI_69_DATA */ + 0x00080004, /* DENALI_PI_70_DATA */ 0x00000000, /* DENALI_PI_71_DATA */ 0x03030000, /* DENALI_PI_72_DATA */ 0x0a0a0a03, /* DENALI_PI_73_DATA */ diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-4GB-04EB-928.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-4GB-04EB-928.c index 54b7397921..493dca47b0 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-4GB-04EB-928.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-4GB-04EB-928.c @@ -466,9 +466,9 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PI_65_DATA */ 0x04060002, /* DENALI_PI_66_DATA */ 0x04010401, /* DENALI_PI_67_DATA */ - 0x01080801, /* DENALI_PI_68_DATA */ - 0x04020201, /* DENALI_PI_69_DATA */ - 0x01080804, /* DENALI_PI_70_DATA */ + 0x00080801, /* DENALI_PI_68_DATA */ + 0x00020001, /* DENALI_PI_69_DATA */ + 0x00080004, /* DENALI_PI_70_DATA */ 0x00000000, /* DENALI_PI_71_DATA */ 0x04040000, /* DENALI_PI_72_DATA */ 0x0c0c0c04, /* DENALI_PI_73_DATA */ diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c index e51cd8968d..97346796fe 100644 --- a/src/soc/rockchip/rk3399/sdram.c +++ b/src/soc/rockchip/rk3399/sdram.c @@ -633,6 +633,7 @@ static int data_training(u32 channel, u32 i, tmp; u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0; u32 rank = sdram_params->ch[channel].rank; + u32 reg_value = 0; /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */ setbits_le32(&denali_phy[927], (1 << 22)); @@ -741,6 +742,28 @@ static int data_training(u32 channel, /* read gate training(LPDDR4,LPDDR3,DDR3 support) */ if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) { + + /* + * The differential signal of DQS needs to keep low level + * before gate training. RPULL will connect 4Kn from PADP + * to VSS and a 4Kn from PADN to VDDQ to ensure it. + * But if it has PHY side ODT connect at this time, + * it will change the DQS signal level. So disable PHY + * side ODT before gate training and restore ODT state + * after gate training. + */ + if (sdram_params->dramtype != LPDDR4) { + reg_value = (read32(&denali_phy[6]) >> 24) & 0x7; + + /* + * phy_dqs_tsel_enable_X 3bits + * DENALI_PHY_6/134/262/390 offset_24 + */ + clrbits_le32(&denali_phy[6], 0x7 << 24); + clrbits_le32(&denali_phy[134], 0x7 << 24); + clrbits_le32(&denali_phy[262], 0x7 << 24); + clrbits_le32(&denali_phy[390], 0x7 << 24); + } for (i = 0; i < rank; i++) { select_per_cs_training_index(channel, i); /* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */ @@ -784,6 +807,18 @@ static int data_training(u32 channel, write32((&denali_pi[175]), 0x00003f7c); } clrbits_le32(&denali_pi[80], 0x3 << 24); + + if (sdram_params->dramtype != LPDDR4) { + /* + * phy_dqs_tsel_enable_X 3bits + * DENALI_PHY_6/134/262/390 offset_24 + */ + tmp = reg_value << 24; + clrsetbits_le32(&denali_phy[6], 0x7 << 24, tmp); + clrsetbits_le32(&denali_phy[134], 0x7 << 24, tmp); + clrsetbits_le32(&denali_phy[262], 0x7 << 24, tmp); + clrsetbits_le32(&denali_phy[390], 0x7 << 24, tmp); + } } /* read leveling(LPDDR4,LPDDR3,DDR3 support) */ |