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-rw-r--r--src/soc/intel/apollolake/include/soc/smbus.h5
-rw-r--r--src/soc/intel/cannonlake/include/soc/smbus.h5
-rw-r--r--src/soc/intel/icelake/include/soc/smbus.h5
-rw-r--r--src/soc/intel/skylake/include/soc/smbus.h7
-rw-r--r--src/soc/intel/tigerlake/include/soc/smbus.h5
5 files changed, 26 insertions, 1 deletions
diff --git a/src/soc/intel/apollolake/include/soc/smbus.h b/src/soc/intel/apollolake/include/soc/smbus.h
index 4b252d61a9..965e8bc264 100644
--- a/src/soc/intel/apollolake/include/soc/smbus.h
+++ b/src/soc/intel/apollolake/include/soc/smbus.h
@@ -21,8 +21,13 @@
#define TCO_TIMEOUT (1 << 3)
#define TCO2_STS 0x06
#define TCO_STS_SECOND_TO (1 << 1)
+#define TCO_INTRD_DET (1 << 0)
#define TCO1_CNT 0x08
#define TCO_LOCK (1 << 12)
#define TCO_TMR_HLT (1 << 11)
+#define TCO2_CNT 0x0A
+#define TCO_INTRD_SEL_MASK (3 << 1)
+#define TCO_INTRD_SEL_SMI (1 << 2)
+#define TCO_INTRD_SEL_INT (1 << 1)
#endif
diff --git a/src/soc/intel/cannonlake/include/soc/smbus.h b/src/soc/intel/cannonlake/include/soc/smbus.h
index 54d0d6cfbf..60d155783e 100644
--- a/src/soc/intel/cannonlake/include/soc/smbus.h
+++ b/src/soc/intel/cannonlake/include/soc/smbus.h
@@ -24,9 +24,14 @@
#define TCO_TIMEOUT (1 << 3)
#define TCO2_STS 0x06
#define TCO_STS_SECOND_TO (1 << 1)
+#define TCO_INTRD_DET (1 << 0)
#define TCO1_CNT 0x08
#define TCO_LOCK (1 << 12)
#define TCO_TMR_HLT (1 << 11)
+#define TCO2_CNT 0x0A
+#define TCO_INTRD_SEL_MASK (3 << 1)
+#define TCO_INTRD_SEL_SMI (1 << 2)
+#define TCO_INTRD_SEL_INT (1 << 1)
/*
* Default slave address value for PCH. This value is set to match default
diff --git a/src/soc/intel/icelake/include/soc/smbus.h b/src/soc/intel/icelake/include/soc/smbus.h
index 9d8fe46b64..2277ca914e 100644
--- a/src/soc/intel/icelake/include/soc/smbus.h
+++ b/src/soc/intel/icelake/include/soc/smbus.h
@@ -21,9 +21,14 @@
#define TCO_TIMEOUT (1 << 3)
#define TCO2_STS 0x06
#define TCO_STS_SECOND_TO (1 << 1)
+#define TCO_INTRD_DET (1 << 0)
#define TCO1_CNT 0x08
#define TCO_LOCK (1 << 12)
#define TCO_TMR_HLT (1 << 11)
+#define TCO2_CNT 0x0A
+#define TCO_INTRD_SEL_MASK (3 << 1)
+#define TCO_INTRD_SEL_SMI (1 << 2)
+#define TCO_INTRD_SEL_INT (1 << 1)
/*
* Default slave address value for PCH. This value is set to match default
diff --git a/src/soc/intel/skylake/include/soc/smbus.h b/src/soc/intel/skylake/include/soc/smbus.h
index ee257ea613..216e864dbc 100644
--- a/src/soc/intel/skylake/include/soc/smbus.h
+++ b/src/soc/intel/skylake/include/soc/smbus.h
@@ -23,10 +23,15 @@
#define TCO1_STS 0x04
#define TCO_TIMEOUT (1 << 3)
#define TCO2_STS 0x06
-#define TCO_STS_SECOND_TO 0x02
+#define TCO_STS_SECOND_TO (1 << 1)
+#define TCO_INTRD_DET (1 << 0)
#define TCO1_CNT 0x08
#define TCO_LOCK (1 << 12)
#define TCO_TMR_HLT (1 << 11)
+#define TCO2_CNT 0x0A
+#define TCO_INTRD_SEL_MASK (3 << 1)
+#define TCO_INTRD_SEL_SMI (1 << 2)
+#define TCO_INTRD_SEL_INT (1 << 1)
/* SMBus I/O bits. */
#define SMBUS_SLAVE_ADDR 0x24
diff --git a/src/soc/intel/tigerlake/include/soc/smbus.h b/src/soc/intel/tigerlake/include/soc/smbus.h
index 50ea044e53..0ad565a613 100644
--- a/src/soc/intel/tigerlake/include/soc/smbus.h
+++ b/src/soc/intel/tigerlake/include/soc/smbus.h
@@ -29,9 +29,14 @@
#define TCO_TIMEOUT (1 << 3)
#define TCO2_STS 0x06
#define TCO_STS_SECOND_TO (1 << 1)
+#define TCO_INTRD_DET (1 << 0)
#define TCO1_CNT 0x08
#define TCO_LOCK (1 << 12)
#define TCO_TMR_HLT (1 << 11)
+#define TCO2_CNT 0x0A
+#define TCO_INTRD_SEL_MASK (3 << 1)
+#define TCO_INTRD_SEL_SMI (1 << 2)
+#define TCO_INTRD_SEL_INT (1 << 1)
/*
* Default slave address value for PCH. This value is set to match default