diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/tyan/s1846/Config.lb | 37 | ||||
| -rw-r--r-- | src/mainboard/tyan/s1846/auto.c | 32 | ||||
| -rw-r--r-- | src/southbridge/intel/i82371eb/Config.lb | 25 | ||||
| -rw-r--r-- | src/southbridge/intel/i82371eb/i82371eb.c | 32 | ||||
| -rw-r--r-- | src/southbridge/intel/i82371eb/i82371eb.h | 32 | ||||
| -rw-r--r-- | src/southbridge/intel/i82371eb/i82371eb_smbus.c | 2 |
6 files changed, 152 insertions, 8 deletions
diff --git a/src/mainboard/tyan/s1846/Config.lb b/src/mainboard/tyan/s1846/Config.lb index c63d895de8..7d8a3cc013 100644 --- a/src/mainboard/tyan/s1846/Config.lb +++ b/src/mainboard/tyan/s1846/Config.lb @@ -126,10 +126,37 @@ dir /pc80 config chip.h # TODO. -chip northbridge/intel/i440bx - device pci_domain 0 on - end - chip cpu/intel/slot_2 - end +chip northbridge/intel/i440bx # Northbridge + device pci_domain 0 on + device pci 0.0 on end # Host bridge + device pci 1.0 off end # PCI bridge TODO: AGP bridge? + # device pci 7.0 on end # ISA bridge + chip southbridge/intel/i82371eb # Southbridge + device pci 7.0 on # ISA bridge ??? + chip superio/nsc/pc87309 # Super I/O + device pnp 2e.0 on end # Floppy + device pnp 2e.1 on end # Parallel port + device pnp 2e.2 on end # Com2 + device pnp 2e.3 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 on end # Power mgmt. + device pnp 2e.5 on end # Mouse + device pnp 2e.6 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 # ??? + end + end + device pci 7.1 on end # IDE + device pci 7.2 on end # USB + device pci 7.3 on end # ACPI + end + end + end + chip cpu/intel/slot_2 + end end diff --git a/src/mainboard/tyan/s1846/auto.c b/src/mainboard/tyan/s1846/auto.c index 26ed148b10..35acfe94ff 100644 --- a/src/mainboard/tyan/s1846/auto.c +++ b/src/mainboard/tyan/s1846/auto.c @@ -49,6 +49,19 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) #include "northbridge/intel/i440bx/debug.c" #include "sdram/generic_sdram.c" +static void enable_mainboard_devices(void) +{ + device_t dev; + + dev = pci_locate_device(PCI_ID(0x8086, 0x7110), 0); + + if (dev == PCI_DEV_INVALID) { + die("Southbridge not found!\n"); + } else { + print_debug("Southbridge found!\n"); + } +} + static void main(unsigned long bist) { static const struct mem_controller memctrl[] = { @@ -75,12 +88,27 @@ static void main(unsigned long bist) /* Halt if there was a built in self test failure. */ report_bist_failure(bist); + enable_mainboard_devices(); + enable_smbus(); dump_spd_registers(&memctrl[0]); sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl); - /* Check 64 MB of RAM. */ - ram_check(0x00000000, 0x04000000); + /* Check whether RAM is working. + * + * Do _not_ check the area from 640 KB - 1 MB, as that's not really + * RAM, but rather reserved for various other things: + * + * - 640 KB 768 KB: Video Buffer Area + * - 768 KB 896 KB: Expansion Area + * - 896 KB 960 KB: Extended System BIOS Area + * - 960 KB 1 MB: Memory (BIOS Area) - System BIOS Area + * + * Trying to check these areas will fail. + */ + /* TODO: This is currently hardcoded to check 64 MB. */ + ram_check(0x00000000, 0x0009ffff); /* 0 - 640 KB */ + ram_check(0x00100000, 0x007c0000); /* 1 MB - 64 MB */ } diff --git a/src/southbridge/intel/i82371eb/Config.lb b/src/southbridge/intel/i82371eb/Config.lb new file mode 100644 index 0000000000..163e846a10 --- /dev/null +++ b/src/southbridge/intel/i82371eb/Config.lb @@ -0,0 +1,25 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config chip.h + +driver i82371eb.o +driver i82371eb_smbus.o + diff --git a/src/southbridge/intel/i82371eb/i82371eb.c b/src/southbridge/intel/i82371eb/i82371eb.c new file mode 100644 index 0000000000..2073a82eee --- /dev/null +++ b/src/southbridge/intel/i82371eb/i82371eb.c @@ -0,0 +1,32 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "i82371eb.h" + +void i82371eb_enable(device_t dev) +{ + /* TODO. */ +} + +struct chip_operations southbridge_intel_i82371eb_ops = { + CHIP_NAME("Intel 82371EB Southbridge") + .enable_dev = i82371eb_enable, +}; diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h new file mode 100644 index 0000000000..275eee6937 --- /dev/null +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -0,0 +1,32 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef I82371EB_H +#define I82371EB_H + +#ifndef __ROMCC__ + +#include "chip.h" + +void i82371eb_enable(device_t dev); + +#endif + +#endif /* I82371EB_H */ diff --git a/src/southbridge/intel/i82371eb/i82371eb_smbus.c b/src/southbridge/intel/i82371eb/i82371eb_smbus.c index 6d640b6d56..07c4bb07f0 100644 --- a/src/southbridge/intel/i82371eb/i82371eb_smbus.c +++ b/src/southbridge/intel/i82371eb/i82371eb_smbus.c @@ -39,5 +39,5 @@ static struct device_operations smbus_ops = { static struct pci_driver smbus_driver __pci_driver = { .ops = &smbus_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_INTEL_440BX_SMB, + .device = 0x7111, // FIXME? }; |