diff options
Diffstat (limited to 'src')
46 files changed, 72 insertions, 79 deletions
diff --git a/src/include/device/device.h b/src/include/device/device.h index f24e4b2157..cb37c096e4 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -321,16 +321,9 @@ static inline DEVTREE_CONST void *config_of(const struct device *dev) devtree_die(); } -static inline DEVTREE_CONST void *config_of_path(pci_devfn_t devfn) +static inline DEVTREE_CONST void *config_of_soc(void) { - const struct device *dev = pcidev_path_on_root(devfn); - if (dev) - return config_of(dev); - - devtree_bug(__func__, devfn); - - dev = dev_find_slot(0, devfn); - return config_of(dev); + return config_of(pcidev_on_root(0, 0)); } void scan_smbus(struct device *bus); diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index 6b3423b886..89e692741e 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -221,7 +221,7 @@ static unsigned long mainboard_write_acpi_tables( static void mainboard_enable(struct device *dev) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); mainboard_set_power_limits(conf); diff --git a/src/mainboard/google/hatch/variants/akemi/variant.c b/src/mainboard/google/hatch/variants/akemi/variant.c index 0717e810ce..c648a527f5 100644 --- a/src/mainboard/google/hatch/variants/akemi/variant.c +++ b/src/mainboard/google/hatch/variants/akemi/variant.c @@ -23,7 +23,7 @@ void variant_devtree_update(void) uint32_t sku_id; struct device *emmc_host; struct device *ssd_host; - config_t *cfg = config_of_path(SA_DEVFN_ROOT); + config_t *cfg = config_of_soc(); emmc_host = pcidev_path_on_root(PCH_DEVFN_EMMC); ssd_host = pcidev_path_on_root(PCH_DEVFN_SATA); diff --git a/src/mainboard/google/hatch/variants/kindred/variant.c b/src/mainboard/google/hatch/variants/kindred/variant.c index 6cd017bf60..1e1d083c25 100644 --- a/src/mainboard/google/hatch/variants/kindred/variant.c +++ b/src/mainboard/google/hatch/variants/kindred/variant.c @@ -23,7 +23,7 @@ void variant_devtree_update(void) uint32_t sku_id; struct device *emmc_host; struct device *ssd_host; - config_t *cfg = config_of_path(SA_DEVFN_ROOT); + config_t *cfg = config_of_soc(); emmc_host = pcidev_path_on_root(PCH_DEVFN_EMMC); ssd_host = pcidev_path_on_root(PCH_DEVFN_SATA); diff --git a/src/mainboard/google/poppy/variants/atlas/mainboard.c b/src/mainboard/google/poppy/variants/atlas/mainboard.c index 9c4b2bc75d..e1538c67b6 100644 --- a/src/mainboard/google/poppy/variants/atlas/mainboard.c +++ b/src/mainboard/google/poppy/variants/atlas/mainboard.c @@ -39,7 +39,7 @@ static uint32_t get_pl2(void) /* Override dev tree settings per board */ void variant_devtree_update(void) { - config_t *cfg = config_of_path(SA_DEVFN_ROOT); + config_t *cfg = config_of_soc(); /* Update PL2 based on CPU */ cfg->tdp_pl2_override = get_pl2(); diff --git a/src/mainboard/google/poppy/variants/nami/mainboard.c b/src/mainboard/google/poppy/variants/nami/mainboard.c index e48a952022..e3855bd794 100644 --- a/src/mainboard/google/poppy/variants/nami/mainboard.c +++ b/src/mainboard/google/poppy/variants/nami/mainboard.c @@ -241,7 +241,7 @@ void variant_devtree_update(void) uint8_t pl2_id = PL2_ID_DEFAULT; struct device *spi_fpmcu = PCH_DEV_GSPI1; - config_t *cfg = config_of_path(SA_DEVFN_ROOT); + config_t *cfg = config_of_soc(); switch (sku_id) { case SKU_0_SONA: diff --git a/src/mainboard/google/poppy/variants/nautilus/mainboard.c b/src/mainboard/google/poppy/variants/nautilus/mainboard.c index 9aa6b724dd..b78ec82aeb 100644 --- a/src/mainboard/google/poppy/variants/nautilus/mainboard.c +++ b/src/mainboard/google/poppy/variants/nautilus/mainboard.c @@ -44,7 +44,7 @@ void variant_devtree_update(void) uint16_t abase; uint32_t val32; - config_t *cfg = config_of_path(SA_DEVFN_ROOT); + config_t *cfg = config_of_soc(); switch (sku_id) { case SKU_0_NAUTILUS: diff --git a/src/mainboard/google/poppy/variants/nocturne/mainboard.c b/src/mainboard/google/poppy/variants/nocturne/mainboard.c index 7b6b28b0ba..3743cf70b1 100644 --- a/src/mainboard/google/poppy/variants/nocturne/mainboard.c +++ b/src/mainboard/google/poppy/variants/nocturne/mainboard.c @@ -40,7 +40,7 @@ static uint32_t get_pl2(void) /* Override dev tree settings per board */ void variant_devtree_update(void) { - config_t *cfg = config_of_path(SA_DEVFN_ROOT); + config_t *cfg = config_of_soc(); /* Update PL2 based on CPU */ cfg->tdp_pl2_override = get_pl2(); diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index f729f3139e..7163884365 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -90,7 +90,7 @@ acpi_cstate_t *soc_get_cstate_map(size_t *entries) void acpi_create_gnvs(struct global_nvs_t *gnvs) { struct soc_intel_apollolake_config *cfg; - cfg = config_of_path(SA_DEVFN_ROOT); + cfg = config_of_soc(); /* Clear out GNVS. */ memset(gnvs, 0, sizeof(*gnvs)); @@ -152,7 +152,7 @@ int soc_madt_sci_irq_polarity(int sci) void soc_fill_fadt(acpi_fadt_t *fadt) { const struct soc_intel_apollolake_config *cfg; - cfg = config_of_path(SA_DEVFN_ROOT); + cfg = config_of_soc(); fadt->pm_tmr_blk = ACPI_BASE_ADDRESS + PM1_TMR; diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index b7159efaec..8e516f8a84 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -300,7 +300,7 @@ static void set_power_limits(void) uint32_t tdp, min_power, max_power; uint32_t pl2_val; - cfg = config_of_path(SA_DEVFN_ROOT); + cfg = config_of_soc(); if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) { printk(BIOS_INFO, "Skip the RAPL settings.\n"); @@ -364,7 +364,7 @@ static void set_sci_irq(void) struct soc_intel_apollolake_config *cfg; uint32_t scis; - cfg = config_of_path(SA_DEVFN_ROOT); + cfg = config_of_soc(); /* Change only if a device tree entry exists. */ if (cfg->sci_irq) { diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 3f06026336..33496273d2 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -296,7 +296,7 @@ void cpu_lock_sgx_memory(void) int soc_fill_sgx_param(struct sgx_param *sgx_param) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); sgx_param->enable = conf->sgx_enable; return 0; diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index 905fa64571..77711ebf26 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -35,7 +35,7 @@ void *cbmem_top(void) if (!CONFIG(SOC_INTEL_GLK)) return tolum; - config = config_of_path(PCH_DEVFN_LPC); + config = config_of_soc(); /* FSP allocates 2x PRMRR Size Memory for alignment */ if (config->sgx_enable) diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 84b61da6b1..23e9732e91 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -148,7 +148,7 @@ void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) { DEVTREE_CONST struct soc_intel_apollolake_config *config; - config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc(); /* Assign to out variable */ *dw0 = config->gpe0_dw1; diff --git a/src/soc/intel/apollolake/pnpconfig.c b/src/soc/intel/apollolake/pnpconfig.c index 0e9e93118a..274f630a71 100644 --- a/src/soc/intel/apollolake/pnpconfig.c +++ b/src/soc/intel/apollolake/pnpconfig.c @@ -39,7 +39,7 @@ static void pnp_settings(void *unused) const struct pnpconfig *pnpconfigarr; struct soc_intel_apollolake_config *config; - config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc(); switch (config->pnp_settings) { case PNP_PERF: diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 29498656dc..8418919bd2 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -95,7 +95,7 @@ static void soc_early_romstage_init(void) static void configure_thermal_target(void) { msr_t msr; - const config_t *conf = config_of_path(SA_DEVFN_ROOT); + const config_t *conf = config_of_soc(); if (!conf->tcc_offset) return; @@ -269,7 +269,7 @@ static void soc_memory_init_params(FSPM_UPD *mupd) /* Only for GLK */ FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - const config_t *config = config_of_path(PCH_DEVFN_LPC); + const config_t *config = config_of_soc(); m_cfg->PrmrrSize = config->PrmrrSize; diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 705bc0089e..7acde68db1 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -390,7 +390,7 @@ static void generate_C_state_entries(void) int *set; int i; - config_t *config = config_of_path(SA_DEVFN_ROOT); + config_t *config = config_of_soc(); if (config->s0ix_enable) set = cstate_set_s0ix; diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 54a695eec1..8fe66dce5b 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -196,7 +196,7 @@ static int pcode_mailbox_write(u32 command, u32 data) static void initialize_vr_config(void) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); msr_t msr; printk(BIOS_DEBUG, "Initializing VR config.\n"); @@ -450,7 +450,7 @@ static void configure_c_states(void) static void configure_thermal_target(void) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); msr_t msr; diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/romstage/pch.c index 0bd4ccd471..af8ea53dea 100644 --- a/src/soc/intel/broadwell/romstage/pch.c +++ b/src/soc/intel/broadwell/romstage/pch.c @@ -78,7 +78,7 @@ static void pch_enable_lpc(void) /* Lookup device tree in romstage */ const config_t *config; - config = config_of_path(PCH_DEVFN_LPC); + config = config_of_soc(); pci_write_config32(PCH_DEV_LPC, LPC_GEN1_DEC, config->gen1_dec); pci_write_config32(PCH_DEV_LPC, LPC_GEN2_DEC, config->gen2_dec); diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 89770c0586..6846594ebf 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -145,7 +145,7 @@ acpi_cstate_t *soc_get_cstate_map(size_t *entries) int *set; int i; - config_t *config = config_of_path(SA_DEVFN_ROOT); + config_t *config = config_of_soc(); int is_s0ix_enable = config->s0ix_enable; @@ -166,7 +166,7 @@ acpi_cstate_t *soc_get_cstate_map(size_t *entries) void soc_power_states_generation(int core_id, int cores_per_package) { - config_t *config = config_of_path(SA_DEVFN_ROOT); + config_t *config = config_of_soc(); /* Generate P-state tables */ if (config->eist_enable) @@ -177,7 +177,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) { const uint16_t pmbase = ACPI_BASE_ADDRESS; const struct soc_intel_cannonlake_config *config; - config = config_of_path(PCH_DEVFN_LPC); + config = config_of_soc(); if (!config->PmTimerDisabled) { fadt->pm_tmr_blk = pmbase + PM1_TMR; @@ -202,7 +202,7 @@ uint32_t soc_read_sci_irq_select(void) void acpi_create_gnvs(struct global_nvs_t *gnvs) { const struct soc_intel_cannonlake_config *config; - config = config_of_path(PCH_DEVFN_LPC); + config = config_of_soc(); /* Set unknown wake source */ gnvs->pm1i = -1; diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index c0810fb2ea..0ce2f1aca7 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -170,7 +170,7 @@ void cnl_configure_pads(const struct pad_config *cfg, size_t num_pads) static void soc_fill_gpio_pm_configuration(void) { uint8_t value[TOTAL_GPIO_COMM]; - const config_t *config = config_of_path(SA_DEVFN_ROOT); + const config_t *config = config_of_soc(); if (config->gpio_override_pm) memcpy(value, config->gpio_pm, sizeof(uint8_t) * diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 0f4d52e790..c58b9ad693 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -106,7 +106,7 @@ void set_power_limits(u8 power_limit_1_time) unsigned int tdp, min_power, max_power, max_time, tdp_pl2, tdp_pl1; u8 power_limit_1_val; - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1; @@ -234,7 +234,7 @@ static void soc_fsp_load(void) static void configure_isst(void) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); msr_t msr; if (conf->speed_shift_enable) { @@ -259,7 +259,7 @@ static void configure_isst(void) static void configure_misc(void) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); msr_t msr; msr = rdmsr(IA32_MISC_ENABLE); @@ -361,7 +361,7 @@ static void configure_c_states(void) static void configure_thermal_target(void) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); msr_t msr; /* Set TCC activation offset if supported */ @@ -387,7 +387,7 @@ static void enable_pm_timer_emulation(void) const struct soc_intel_cannonlake_config *config; msr_t msr; - config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc(); /* Enable PM timer emulation only if ACPI PM timer is disabled */ if (!config->PmTimerDisabled) diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index c99653b75a..115b73254e 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -84,7 +84,7 @@ static void pch_finalize(void) * point and hence removed from the root bus. pcidev_path_on_root thus * returns NULL for PCH_DEV_PMC device. */ - config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc(); pmcbase = pmc_mmio_regs(); if (config->PmTimerDisabled) { reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 76d40aa624..b580620d70 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -99,7 +99,7 @@ static void parse_devicetree_param(const config_t *config, FSP_S_CONFIG *params) static void parse_devicetree(FSP_S_CONFIG *params) { - const config_t *config = config_of_path(SA_DEVFN_ROOT); + const config_t *config = config_of_soc(); parse_devicetree_param(config, params); } @@ -145,7 +145,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig; struct device *dev; - config_t *config = config_of_path(SA_DEVFN_ROOT); + config_t *config = config_of_soc(); /* Parse device tree and enable/disable devices */ parse_devicetree(params); diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c index b9f455ff68..c0bb9ae296 100644 --- a/src/soc/intel/cannonlake/pmc.c +++ b/src/soc/intel/cannonlake/pmc.c @@ -102,7 +102,7 @@ static void config_deep_sx(uint32_t deepsx_config) static void pmc_init(void *unused) { - const config_t *config = config_of_path(SA_DEVFN_ROOT); + const config_t *config = config_of_soc(); rtc_init(); diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index 1626e300d8..a543861406 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -175,7 +175,7 @@ uintptr_t soc_read_pmc_base(void) void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) { DEVTREE_CONST struct soc_intel_cannonlake_config *config; - config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc(); /* Assign to out variable */ *dw0 = config->gpe0_dw0; diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index b8ceec0f1d..4d0b241517 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -79,7 +79,7 @@ void smihandler_soc_at_finalize(void) { const struct soc_intel_cannonlake_config *config; - config = config_of_path(PCH_DEVFN_CSE); + config = config_of_soc(); if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM)) pch_disable_heci(); diff --git a/src/soc/intel/common/block/chip/chip.c b/src/soc/intel/common/block/chip/chip.c index 9e74803e1a..5ab8f6b07d 100644 --- a/src/soc/intel/common/block/chip/chip.c +++ b/src/soc/intel/common/block/chip/chip.c @@ -22,7 +22,7 @@ const struct soc_intel_common_config *chip_get_common_soc_structure(void) const struct soc_intel_common_config *soc_config; const config_t *config; - config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc(); soc_config = &config->common_soc_config; return soc_config; diff --git a/src/soc/intel/fsp_broadwell_de/iou_complto.c b/src/soc/intel/fsp_broadwell_de/iou_complto.c index f998d97547..b092f53875 100644 --- a/src/soc/intel/fsp_broadwell_de/iou_complto.c +++ b/src/soc/intel/fsp_broadwell_de/iou_complto.c @@ -24,7 +24,7 @@ static void iou_init(struct device *dev) { /* Use config from device always present in static devicetree. */ - const config_t *config = config_of_path(SOC_DEV_FUNC); + const config_t *config = config_of_soc(); u16 devctl2; /* pcie completion timeout diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index c61d877d1c..4089679d1c 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -138,7 +138,7 @@ acpi_cstate_t *soc_get_cstate_map(size_t *entries) int *set; int i; - config_t *config = config_of_path(SA_DEVFN_ROOT); + config_t *config = config_of_soc(); int is_s0ix_enable = config->s0ix_enable; @@ -159,7 +159,7 @@ acpi_cstate_t *soc_get_cstate_map(size_t *entries) void soc_power_states_generation(int core_id, int cores_per_package) { - config_t *config = config_of_path(SA_DEVFN_ROOT); + config_t *config = config_of_soc(); if (config->eist_enable) /* Generate P-state tables */ @@ -170,7 +170,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) { const uint16_t pmbase = ACPI_BASE_ADDRESS; - config_t *config = config_of_path(SA_DEVFN_ROOT); + config_t *config = config_of_soc(); if (!config->PmTimerDisabled) { fadt->pm_tmr_blk = pmbase + PM1_TMR; @@ -194,7 +194,7 @@ uint32_t soc_read_sci_irq_select(void) void acpi_create_gnvs(struct global_nvs_t *gnvs) { - config_t *config = config_of_path(SA_DEVFN_ROOT); + config_t *config = config_of_soc(); /* Set unknown wake source */ gnvs->pm1i = -1; diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c index e71c573f98..2bb908c064 100644 --- a/src/soc/intel/icelake/chip.c +++ b/src/soc/intel/icelake/chip.c @@ -107,7 +107,7 @@ const char *soc_acpi_name(const struct device *dev) static void soc_fill_gpio_pm_configuration(void) { uint8_t value[TOTAL_GPIO_COMM]; - const config_t *config = config_of_path(SA_DEVFN_ROOT); + const config_t *config = config_of_soc(); if (config->gpio_override_pm) memcpy(value, config->gpio_pm, sizeof(uint8_t) * diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index 8a65ccf5d3..0ecccb94e5 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -40,7 +40,7 @@ static void soc_fsp_load(void) static void configure_isst(void) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); msr_t msr; if (conf->speed_shift_enable) { @@ -67,7 +67,7 @@ static void configure_misc(void) { msr_t msr; - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 0); /* Fast String enable */ diff --git a/src/soc/intel/icelake/finalize.c b/src/soc/intel/icelake/finalize.c index 086787d9df..a70b5a1ed4 100644 --- a/src/soc/intel/icelake/finalize.c +++ b/src/soc/intel/icelake/finalize.c @@ -83,7 +83,7 @@ static void pch_finalize(void) * point and hence removed from the root bus. pcidev_path_on_root thus * returns NULL for PCH_DEV_PMC device. */ - config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc(); pmcbase = pmc_mmio_regs(); if (config->PmTimerDisabled) { reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index e31e47bf57..8819e7d033 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -31,7 +31,7 @@ static void parse_devicetree(FSP_S_CONFIG *params) { const struct soc_intel_icelake_config *config; - config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc(); for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++) params->SerialIoI2cMode[i] = config->SerialIoI2cMode[i]; @@ -69,7 +69,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) struct device *dev; struct soc_intel_icelake_config *config; - config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc(); /* Parse device tree and enable/disable devices */ parse_devicetree(params); diff --git a/src/soc/intel/icelake/pmc.c b/src/soc/intel/icelake/pmc.c index 28fc01d029..6348d28b25 100644 --- a/src/soc/intel/icelake/pmc.c +++ b/src/soc/intel/icelake/pmc.c @@ -84,7 +84,7 @@ static void config_deep_sx(uint32_t deepsx_config) static void pmc_init(void *unused) { - const config_t *config = config_of_path(SA_DEVFN_ROOT); + const config_t *config = config_of_soc(); rtc_init(); diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index a70840b527..c20da5018a 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -174,7 +174,7 @@ void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) { DEVTREE_CONST struct soc_intel_icelake_config *config; - config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc(); /* Assign to out variable */ *dw0 = config->gpe0_dw0; diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c index a78c8a49cf..5bf34213f0 100644 --- a/src/soc/intel/icelake/romstage/fsp_params.c +++ b/src/soc/intel/icelake/romstage/fsp_params.c @@ -79,7 +79,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) const struct soc_intel_icelake_config *config; FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc(); soc_memory_init_params(m_cfg, config); diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c index 8db2c3bbb4..b7c37d4aa7 100644 --- a/src/soc/intel/icelake/smihandler.c +++ b/src/soc/intel/icelake/smihandler.c @@ -76,7 +76,7 @@ void smihandler_soc_at_finalize(void) { const struct soc_intel_icelake_config *config; - config = config_of_path(PCH_DEVFN_CSE); + config = config_of_soc(); if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM)) pch_disable_heci(); diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index a64fed4868..cd654d74de 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -93,7 +93,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version) "Microcode file (rmu.bin) not found."); /* Locate the configuration data from devicetree.cb */ - config = config_of_path(LPC_DEV_FUNC); + config = config_of_soc(); /* Update the architectural UPD values. */ aupd = &fspm_upd->FspmArchUpd; diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index d67b502ac8..de37341a08 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -172,7 +172,7 @@ static int get_cores_per_package(void) static void acpi_create_gnvs(global_nvs_t *gnvs) { - const struct soc_intel_skylake_config *config = config_of_path(PCH_DEVFN_LPC); + const struct soc_intel_skylake_config *config = config_of_soc(); /* Set unknown wake source */ gnvs->pm1i = -1; @@ -232,7 +232,7 @@ unsigned long acpi_fill_madt(unsigned long current) void acpi_fill_fadt(acpi_fadt_t *fadt) { const uint16_t pmbase = ACPI_BASE_ADDRESS; - config_t *config = config_of_path(SA_DEVFN_ROOT); + config_t *config = config_of_soc(); /* Use ACPI 3.0 revision */ fadt->header.revision = get_acpi_table_revision(FADT); @@ -503,7 +503,7 @@ void generate_cpu_entries(struct device *device) int totalcores = dev_count_cpu(); int cores_per_package = get_cores_per_package(); int numcpus = totalcores/cores_per_package; - config_t *config = config_of_path(SA_DEVFN_ROOT); + config_t *config = config_of_soc(); int is_s0ix_enable = config->s0ix_enable; printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", @@ -674,7 +674,7 @@ void southbridge_inject_dsdt(struct device *device) /* Save wake source information for calculating ACPI _SWS values */ int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) { - const struct soc_intel_skylake_config *config = config_of_path(PCH_DEVFN_LPC); + const struct soc_intel_skylake_config *config = config_of_soc(); struct chipset_power_state *ps; static uint32_t gpe0_sts[GPE0_REG_MAX]; uint32_t pm1_en; diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 462285c2a0..55fedd3cf5 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -237,7 +237,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) uintptr_t vbt_data = (uintptr_t)vbt_get(); int i; - config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc(); mainboard_silicon_init_params(params); /* Set PsysPmax if it is available from DT */ diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 0d49d28d3d..5424c91c58 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -117,7 +117,7 @@ void set_power_limits(u8 power_limit_1_time) unsigned int tdp, min_power, max_power, max_time, tdp_pl2, tdp_pl1; u8 power_limit_1_val; - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1; @@ -240,7 +240,7 @@ void set_power_limits(u8 power_limit_1_time) static void configure_thermal_target(void) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); msr_t msr; @@ -260,7 +260,7 @@ static void configure_thermal_target(void) static void configure_isst(void) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); msr_t msr; @@ -286,7 +286,7 @@ static void configure_isst(void) static void configure_misc(void) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); msr_t msr; @@ -562,7 +562,7 @@ void cpu_lock_sgx_memory(void) int soc_fill_sgx_param(struct sgx_param *sgx_param) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); sgx_param->enable = conf->sgx_enable; return 0; diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index ffe060518e..ab9297fe92 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -188,7 +188,7 @@ BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL); */ static void pm1_handle_wake_pin(void *unused) { - const config_t *conf = config_of_path(SA_DEVFN_ROOT); + const config_t *conf = config_of_soc(); /* If WAKE# pin is enabled, bail out early. */ if (conf->deep_sx_config & DSX_EN_WAKE_PIN) diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 90f1b038e0..329cea9621 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -177,7 +177,7 @@ void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) { DEVTREE_CONST struct soc_intel_skylake_config *config; - config = config_of_path(PCH_DEVFN_PMC); + config = config_of_soc(); /* Assign to out variable */ *dw0 = config->gpe0_dw0; diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index a8bbfb633d..f354af3442 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -43,7 +43,7 @@ void soc_pre_ram_init(struct romstage_params *params) /* Program MCHBAR and DMIBAR */ systemagent_early_init(); - config = config_of_path(PCH_DEVFN_LPC); + config = config_of_soc(); /* Force a full memory train if RMT is enabled */ params->disable_saved_data = config->Rmt; @@ -57,7 +57,7 @@ void soc_memory_init_params(struct romstage_params *params, /* Set the parameters for MemoryInit */ - config = config_of_path(PCH_DEVFN_LPC); + config = config_of_soc(); /* * Set IGD stolen size to 64MB. The FBC hardware for skylake does not diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index deda53312c..af89441194 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -289,7 +289,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig; - config = config_of_path(PCH_DEVFN_LPC); + config = config_of_soc(); soc_memory_init_params(m_cfg, config); soc_peg_init_params(m_cfg, m_t_cfg, config); diff --git a/src/soc/intel/skylake/romstage/systemagent.c b/src/soc/intel/skylake/romstage/systemagent.c index 9b7ea2470e..bf0d5064e4 100644 --- a/src/soc/intel/skylake/romstage/systemagent.c +++ b/src/soc/intel/skylake/romstage/systemagent.c @@ -29,7 +29,7 @@ static void systemagent_vtd_init(void) const struct device *const igd_dev = pcidev_path_on_root(SA_DEVFN_IGD); const struct soc_intel_skylake_config *config = NULL; - config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc(); if (config->ignore_vtd) return; |