2 files changed, 35 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index c3de4ee802..279551f9e0 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -50,6 +50,7 @@
 #include <soc/systemagent.h>
 #include <spi-generic.h>
 #include <timer.h>
+#include <soc/ramstage.h>
 
 #include "chip.h"
 
@@ -762,6 +763,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
 
 	/* Set VTD feature according to devicetree */
 	silconfig->VtdEnable = cfg->enable_vtd;
+
+	mainboard_silicon_init_params(silconfig);
 }
 
 struct chip_operations soc_intel_apollolake_ops = {
@@ -879,4 +882,10 @@ static void spi_flash_init_cb(void *unused)
 	fast_spi_init();
 }
 
+__weak
+void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig)
+{
+	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
+
 BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_flash_init_cb, NULL);
diff --git a/src/soc/intel/apollolake/include/soc/ramstage.h b/src/soc/intel/apollolake/include/soc/ramstage.h
new file mode 100644
index 0000000000..287f2ff945
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/ramstage.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
+ * Copyright (C) 2019 9elements Agency GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_APOLLOLAKE_RAMSTAGE_H_
+#define _SOC_APOLLOLAKE_RAMSTAGE_H_
+
+#include <fsp/api.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig);
+
+#endif /* _SOC_APOLLOLAKE_RAMSTAGE_H_ */