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-rw-r--r--src/soc/intel/apollolake/acpi/northbridge.asl153
-rw-r--r--src/soc/intel/cannonlake/acpi/northbridge.asl396
-rw-r--r--src/soc/intel/icelake/acpi/northbridge.asl404
-rw-r--r--src/soc/intel/skylake/acpi/systemagent.asl428
-rw-r--r--src/soc/intel/skylake/include/soc/iomap.h3
-rw-r--r--src/soc/intel/tigerlake/acpi/northbridge.asl133
6 files changed, 726 insertions, 791 deletions
diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl
index 2f2a064f1b..027e2a623c 100644
--- a/src/soc/intel/apollolake/acpi/northbridge.asl
+++ b/src/soc/intel/apollolake/acpi/northbridge.asl
@@ -15,112 +15,113 @@
* GNU General Public License for more details.
*/
- Name(_HID, EISAID("PNP0A08")) /* PCIe */
- Name(_CID, EISAID("PNP0A03")) /* PCI */
- Name(_BBN, 0)
+#define BASE_64GB 0x1000000000
+
+Name(_HID, EISAID("PNP0A08")) /* PCIe */
+Name(_CID, EISAID("PNP0A03")) /* PCI */
Device (MCHC)
{
Name (_ADR, 0x00000000) /*Dev0 Func0 */
- OperationRegion (MCHP, PCI_Config, 0x00, 0x100)
- Field (MCHP, DWordAcc, NoLock, Preserve)
- {
- Offset(0x60),
- MCNF, 32, /* PCI MMCONF base */
- Offset (0xA8),
- TUUD, 64, /* Top of Upper Used Memory */
- Offset(0xB4),
- BGSM, 32, /* Base of Graphics Stolen Memory */
- Offset(0xBC),
- TLUD, 32, /* Top of Low Useable DRAM */
- }
+ OperationRegion (MCHP, PCI_Config, 0x00, 0x100)
+ Field (MCHP, DWordAcc, NoLock, Preserve)
+ {
+ Offset(0x60),
+ MCNF, 32, /* PCI MMCONF base */
+ Offset (0xA8),
+ TUUD, 64, /* Top of Upper Used Memory */
+ Offset(0xB4),
+ BGSM, 32, /* Base of Graphics Stolen Memory */
+ Offset(0xBC),
+ TLUD, 32, /* Top of Low Useable DRAM */
+ }
}
-Name (MCRS, ResourceTemplate()
-{
- /* Bus Numbers */
- WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
- 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,,)
-
- /* IO Region 0 */
- DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,,)
-
- /* PCI Config Space */
- Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
-
- /* IO Region 1 */
- DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, 0x01000, 0xffff, 0x0000, 0xf000,,,)
-
- /* VGA memory (0xa0000-0xbffff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
- 0x00020000,,,)
-
- /* Data and GFX stolen memory */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x3be00000, 0x3fffffff, 0x00000000,
- 0x04200000,,, STOM)
-
- /*
- * PCI MMIO Region (TOLUD - PCI extended base MMCONF)
- * This assumes that MMCONF is placed after PCI config space,
- * and that no resources are allocated after the MMCONF region.
- * This works, sicne MMCONF is hardcoded to 0xe00000000.
- */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- NonCacheable, ReadWrite,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000,,, PM01)
-
- /* PCI Memory Region (TOUUD - (TOUUD + ABOVE_4G_MMIO_SIZE)) */
- QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- NonCacheable, ReadWrite,
- 0x00000000, 0x10000, 0x1ffff, 0x00000000,
- 0x10000,,, PM02)
-})
/* Current Resource Settings */
Method (_CRS, 0, Serialized)
{
+ Name (MCRS, ResourceTemplate()
+ {
+ /* Bus Numbers */
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,,)
+
+ /* IO Region 0 */
+ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,,)
+
+ /* PCI Config Space */
+ Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
+
+ /* IO Region 1 */
+ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, 0x01000, 0xffff, 0x0000, 0xf000,,,)
+
+ /* VGA memory (0xa0000-0xbffff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
+ 0x00020000,,,)
+
+ /* Data and GFX stolen memory */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x3be00000, 0x3fffffff, 0x00000000,
+ 0x04200000,,, STOM)
+
+ /*
+ * PCI MMIO Region (TOLUD - PCI extended base MMCONF)
+ * This assumes that MMCONF is placed after PCI config space,
+ * and that no resources are allocated after the MMCONF region.
+ * This works, sicne MMCONF is hardcoded to 0xe00000000.
+ */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ NonCacheable, ReadWrite,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000,,, PM01)
+
+ /* PCI Memory Region (TOUUD - (TOUUD + ABOVE_4G_MMIO_SIZE)) */
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ NonCacheable, ReadWrite,
+ 0x00000000, 0x10000, 0x1ffff, 0x00000000,
+ 0x10000,,, PM02)
+ })
/* Find PCI resource area in MCRS */
- CreateDwordField (MCRS, ^PM01._MIN, PMIN)
- CreateDwordField (MCRS, ^PM01._MAX, PMAX)
- CreateDwordField (MCRS, ^PM01._LEN, PLEN)
+ CreateDwordField (MCRS, PM01._MIN, PMIN)
+ CreateDwordField (MCRS, PM01._MAX, PMAX)
+ CreateDwordField (MCRS, PM01._LEN, PLEN)
/* Read C-Unit PCI CFG Reg. 0xBC for TOLUD (shadow from B-Unit) */
- And(^MCHC.TLUD, 0xFFF00000, PMIN)
+ And(\_SB.PCI0.MCHC.TLUD, 0xFFF00000, PMIN)
/* Read MMCONF base */
- And(^MCHC.MCNF, 0xF0000000, PMAX)
+ And(\_SB.PCI0.MCHC.MCNF, 0xF0000000, PMAX)
/* Calculate PCI MMIO Length */
Add(Subtract(PMAX, PMIN), 1, PLEN)
/* Find GFX resource area in GCRS */
- CreateDwordField(MCRS, ^STOM._MIN, GMIN)
- CreateDwordField(MCRS, ^STOM._MAX, GMAX)
- CreateDwordField(MCRS, ^STOM._LEN, GLEN)
+ CreateDwordField(MCRS, STOM._MIN, GMIN)
+ CreateDwordField(MCRS, STOM._MAX, GMAX)
+ CreateDwordField(MCRS, STOM._LEN, GLEN)
/* Read BGSM */
- And(^MCHC.BGSM, 0xFFF00000, GMIN)
+ And(\_SB.PCI0.MCHC.BGSM, 0xFFF00000, GMIN)
/* Read TOLUD */
- And(^MCHC.TLUD, 0xFFF00000, GMAX)
+ And(\_SB.PCI0.MCHC.TLUD, 0xFFF00000, GMAX)
Decrement(GMAX)
Add(Subtract(GMAX, GMIN), 1, GLEN)
/* Patch PM02 range based on Memory Size */
- CreateQwordField (MCRS, ^PM02._MIN, MMIN)
- CreateQwordField (MCRS, ^PM02._MAX, MMAX)
- CreateQwordField (MCRS, ^PM02._LEN, MLEN)
+ CreateQwordField (MCRS, PM02._MIN, MMIN)
+ CreateQwordField (MCRS, PM02._MAX, MMAX)
+ CreateQwordField (MCRS, PM02._LEN, MLEN)
- Store (^MCHC.TUUD, Local0)
+ Store (\_SB.PCI0.MCHC.TUUD, Local0)
- If (LLessEqual (Local0, 0x1000000000))
+ If (LLessEqual (Local0, BASE_64GB))
{
Store (0, MMIN)
Store (0, MLEN)
diff --git a/src/soc/intel/cannonlake/acpi/northbridge.asl b/src/soc/intel/cannonlake/acpi/northbridge.asl
index 25291163cf..ead5c02a16 100644
--- a/src/soc/intel/cannonlake/acpi/northbridge.asl
+++ b/src/soc/intel/cannonlake/acpi/northbridge.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2017 Intel Corp.
+ * Copyright (C) 2017-2020 Intel Corp.
* (Written by Bora Guvendik <bora.guvendik@intel.com> for Intel Corp.)
*
* This program is free software; you can redistribute it and/or modify
@@ -62,154 +62,154 @@ Device (MCHC)
}
}
-Name (MCRS, ResourceTemplate ()
-{
- /* Bus Numbers */
- WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
- 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100)
-
- /* IO Region 0 */
- DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode,
- EntireRange,
- 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8)
-
- /* PCI Config Space */
- Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
-
- /* IO Region 1 */
- DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode,
- EntireRange,
- 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300)
-
- /* VGA memory (0xa0000-0xbffff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
- 0x00020000)
-
- /* OPROM reserved (0xc0000-0xc3fff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
- 0x00004000)
-
- /* OPROM reserved (0xc4000-0xc7fff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
- 0x00004000)
-
- /* OPROM reserved (0xc8000-0xcbfff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
- 0x00004000)
-
- /* OPROM reserved (0xcc000-0xcffff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
- 0x00004000)
-
- /* OPROM reserved (0xd0000-0xd3fff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
- 0x00004000)
-
- /* OPROM reserved (0xd4000-0xd7fff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
- 0x00004000)
-
- /* OPROM reserved (0xd8000-0xdbfff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
- 0x00004000)
-
- /* OPROM reserved (0xdc000-0xdffff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
- 0x00004000)
-
- /* BIOS Extension (0xe0000-0xe3fff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
- 0x00004000)
-
- /* BIOS Extension (0xe4000-0xe7fff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
- 0x00004000)
-
- /* BIOS Extension (0xe8000-0xebfff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
- 0x00004000)
-
- /* BIOS Extension (0xec000-0xeffff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000ec000, 0x000effff, 0x00000000,
- 0x00004000)
-
- /* System BIOS (0xf0000-0xfffff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
- 0x00010000)
-
- /* PCI Memory Region (TLUD - 0xdfffffff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- NonCacheable, ReadWrite,
- 0x00000000, 0x00000000, 0xdfffffff, 0x00000000,
- 0xE0000000,,, PM01)
-
- /* PCI Memory Region (TUUD - (TUUD + ABOVE_4G_MMIO_SIZE)) */
- QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- NonCacheable, ReadWrite,
- 0x00000000, 0x10000, 0x1ffff, 0x00000000,
- 0x10000,,, PM02)
-
- /* PCH reserved resource (0xfc800000-0xfe7fffff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, PCH_PRESERVED_BASE_ADDRESS, 0xfe7fffff,
- 0x00000000, PCH_PRESERVED_BASE_SIZE)
-
- /* TPM Area (0xfed40000-0xfed47fff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0xfed40000, 0xfed47fff, 0x00000000,
- 0x00008000)
-})
-
Method (_CRS, 0, Serialized)
{
+ Name (MCRS, ResourceTemplate ()
+ {
+ /* Bus Numbers */
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100)
+
+ /* IO Region 0 */
+ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ EntireRange,
+ 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8)
+
+ /* PCI Config Space */
+ Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
+
+ /* IO Region 1 */
+ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ EntireRange,
+ 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300)
+
+ /* VGA memory (0xa0000-0xbffff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
+ 0x00020000)
+
+ /* OPROM reserved (0xc0000-0xc3fff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
+ 0x00004000)
+
+ /* OPROM reserved (0xc4000-0xc7fff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
+ 0x00004000)
+
+ /* OPROM reserved (0xc8000-0xcbfff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
+ 0x00004000)
+
+ /* OPROM reserved (0xcc000-0xcffff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
+ 0x00004000)
+
+ /* OPROM reserved (0xd0000-0xd3fff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
+ 0x00004000)
+
+ /* OPROM reserved (0xd4000-0xd7fff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
+ 0x00004000)
+
+ /* OPROM reserved (0xd8000-0xdbfff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
+ 0x00004000)
+
+ /* OPROM reserved (0xdc000-0xdffff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
+ 0x00004000)
+
+ /* BIOS Extension (0xe0000-0xe3fff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
+ 0x00004000)
+
+ /* BIOS Extension (0xe4000-0xe7fff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
+ 0x00004000)
+
+ /* BIOS Extension (0xe8000-0xebfff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
+ 0x00004000)
+
+ /* BIOS Extension (0xec000-0xeffff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000ec000, 0x000effff, 0x00000000,
+ 0x00004000)
+
+ /* System BIOS (0xf0000-0xfffff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
+ 0x00010000)
+
+ /* PCI Memory Region (TLUD - 0xdfffffff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ NonCacheable, ReadWrite,
+ 0x00000000, 0x00000000, 0xdfffffff, 0x00000000,
+ 0xE0000000,,, PM01)
+
+ /* PCI Memory Region (TUUD - (TUUD + ABOVE_4G_MMIO_SIZE)) */
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ NonCacheable, ReadWrite,
+ 0x00000000, 0x10000, 0x1ffff, 0x00000000,
+ 0x10000,,, PM02)
+
+ /* PCH reserved resource (0xfc800000-0xfe7fffff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, PCH_PRESERVED_BASE_ADDRESS, 0xfe7fffff,
+ 0x00000000, PCH_PRESERVED_BASE_SIZE)
+
+ /* TPM Area (0xfed40000-0xfed47fff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0xfed40000, 0xfed47fff, 0x00000000,
+ 0x00008000)
+ })
+
/* Find PCI resource area in MCRS */
- CreateDwordField (^MCRS, ^PM01._MIN, PMIN)
- CreateDwordField (^MCRS, ^PM01._MAX, PMAX)
- CreateDwordField (^MCRS, ^PM01._LEN, PLEN)
+ CreateDwordField (MCRS, PM01._MIN, PMIN)
+ CreateDwordField (MCRS, PM01._MAX, PMAX)
+ CreateDwordField (MCRS, PM01._LEN, PLEN)
/*
* Fix up PCI memory region
* Start with Top of Lower Usable DRAM
*/
- Store (^MCHC.TLUD, PMIN)
+ Store (\_SB.PCI0.MCHC.TLUD, PMIN)
Add (Subtract (PMAX, PMIN), 1, PLEN)
/* Patch PM02 range based on Memory Size */
- CreateQwordField (^MCRS, ^PM02._MIN, MMIN)
- CreateQwordField (^MCRS, ^PM02._MAX, MMAX)
- CreateQwordField (^MCRS, ^PM02._LEN, MLEN)
+ CreateQwordField (MCRS, PM02._MIN, MMIN)
+ CreateQwordField (MCRS, PM02._MAX, MMAX)
+ CreateQwordField (MCRS, PM02._LEN, MLEN)
- Store (^MCHC.TUUD, Local0)
+ Store (\_SB.PCI0.MCHC.TUUD, Local0)
If (LLessEqual (Local0, BASE_32GB)) {
Store (BASE_32GB, MMIN)
@@ -220,58 +220,42 @@ Method (_CRS, 0, Serialized)
}
Subtract (Add (MMIN, MLEN), 1, MMAX)
- Return (^MCRS)
+ Return (MCRS)
}
-Name (EP_B, 0) /* to store EP BAR */
-Name (MH_B, 0) /* to store MCH BAR */
-Name (PC_B, 0) /* to store PCIe BAR */
-Name (PC_L, 0) /* to store PCIe BAR Length */
-Name (DM_B, 0) /* to store DMI BAR */
-
/* Get MCH BAR */
Method (GMHB, 0, Serialized)
{
- If (LEqual (MH_B, 0)) {
- ShiftLeft (\_SB.PCI0.MCHC.MHBR, 15, MH_B)
- }
- Return (MH_B)
+ ShiftLeft (\_SB.PCI0.MCHC.MHBR, 15, Local0)
+ Return (Local0)
}
/* Get EP BAR */
Method (GEPB, 0, Serialized)
{
- If (LEqual (EP_B, 0)) {
- ShiftLeft (\_SB.PCI0.MCHC.EPBR, 12, EP_B)
- }
- Return (EP_B)
+ ShiftLeft (\_SB.PCI0.MCHC.EPBR, 12, Local0)
+ Return (Local0)
}
/* Get PCIe BAR */
Method (GPCB, 0, Serialized)
{
- If (LEqual (PC_B, 0)) {
- ShiftLeft (\_SB.PCI0.MCHC.PXBR, 26, PC_B)
- }
- Return (PC_B)
+ ShiftLeft (\_SB.PCI0.MCHC.PXBR, 26, Local0)
+ Return (Local0)
}
/* Get PCIe Length */
Method (GPCL, 0, Serialized)
{
- If (LEqual (PC_L, 0)) {
- ShiftRight (0x10000000, \_SB.PCI0.MCHC.PXSZ, PC_L)
- }
- Return (PC_L)
+ ShiftRight (0x10000000, \_SB.PCI0.MCHC.PXSZ, Local0)
+ Return (Local0)
}
/* Get DMI BAR */
Method (GDMB, 0, Serialized)
{
- If (LEqual (DM_B, 0)) {
- ShiftLeft (\_SB.PCI0.MCHC.DIBR, 12, DM_B)
- }
- Return (DM_B)
+ ShiftLeft (\_SB.PCI0.MCHC.DIBR, 12, Local0)
+ Return (Local0)
}
/* PCI Device Resource Consumption */
@@ -280,59 +264,61 @@ Device (PDRC)
Name (_HID, EISAID ("PNP0C02"))
Name (_UID, 1)
- Name (BUF0, ResourceTemplate ()
- {
- /* MCH BAR _BAS will be updated in _CRS below according to
- * B0:D0:F0:Reg.48h
- */
- Memory32Fixed (ReadWrite, 0, 0x08000, MCHB)
-
- /* DMI BAR _BAS will be updated in _CRS below according to
- * B0:D0:F0:Reg.68h
- */
- Memory32Fixed (ReadWrite, 0, 0x01000, DMIB)
-
- /* EP BAR _BAS will be updated in _CRS below according to
- * B0:D0:F0:Reg.40h
- */
- Memory32Fixed (ReadWrite, 0, 0x01000, EGPB)
-
- /* PCI Express BAR _BAS and _LEN will be updated in
- * _CRS below according to B0:D0:F0:Reg.60h
- */
- Memory32Fixed (ReadWrite, 0, 0, PCIX)
-
- /* VTD engine memory range.
- */
- Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE)
-
- /* FLASH range */
- Memory32Fixed (ReadOnly, 0xFF000000, 0x1000000, FIOH)
-
- /* Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) */
- Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000, LIOH)
-
- /* HPET address decode range */
- Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400)
- })
-
Method (_CRS, 0, Serialized)
{
- CreateDwordField (BUF0, ^MCHB._BAS, MBR0)
+ Name (BUF0, ResourceTemplate ()
+ {
+ /* MCH BAR _BAS will be updated in _CRS below according to
+ * B0:D0:F0:Reg.48h
+ */
+ Memory32Fixed (ReadWrite, 0, 0x08000, MCHB)
+
+ /* DMI BAR _BAS will be updated in _CRS below according to
+ * B0:D0:F0:Reg.68h
+ */
+ Memory32Fixed (ReadWrite, 0, 0x01000, DMIB)
+
+ /* EP BAR _BAS will be updated in _CRS below according to
+ * B0:D0:F0:Reg.40h
+ */
+ Memory32Fixed (ReadWrite, 0, 0x01000, EGPB)
+
+ /* PCI Express BAR _BAS and _LEN will be updated in
+ * _CRS below according to B0:D0:F0:Reg.60h
+ */
+ Memory32Fixed (ReadWrite, 0, 0, PCIX)
+
+ /* VTD engine memory range. */
+ Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE)
+
+ /* FLASH range */
+ Memory32Fixed (ReadOnly, 0, CONFIG_ROM_SIZE, FIOH)
+
+ /* Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) */
+ Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000)
+
+ /* HPET address decode range */
+ Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400)
+ })
+
+ CreateDwordField (BUF0, MCHB._BAS, MBR0)
Store (\_SB.PCI0.GMHB (), MBR0)
- CreateDwordField (BUF0, ^DMIB._BAS, DBR0)
+ CreateDwordField (BUF0, DMIB._BAS, DBR0)
Store (\_SB.PCI0.GDMB (), DBR0)
- CreateDwordField (BUF0, ^EGPB._BAS, EBR0)
+ CreateDwordField (BUF0, EGPB._BAS, EBR0)
Store (\_SB.PCI0.GEPB (), EBR0)
- CreateDwordField (BUF0, ^PCIX._BAS, XBR0)
+ CreateDwordField (BUF0, PCIX._BAS, XBR0)
Store (\_SB.PCI0.GPCB (), XBR0)
- CreateDwordField (BUF0, ^PCIX._LEN, XSZ0)
+ CreateDwordField (BUF0, PCIX._LEN, XSZ0)
Store (\_SB.PCI0.GPCL (), XSZ0)
+ CreateDwordField (BUF0, FIOH._BAS, FBR0)
+ Subtract(0x100000000, CONFIG_ROM_SIZE, FBR0)
+
Return (BUF0)
}
}
diff --git a/src/soc/intel/icelake/acpi/northbridge.asl b/src/soc/intel/icelake/acpi/northbridge.asl
index 68c7f9e9fd..684202198a 100644
--- a/src/soc/intel/icelake/acpi/northbridge.asl
+++ b/src/soc/intel/icelake/acpi/northbridge.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2018 Intel Corp.
+ * Copyright (C) 2018-2020 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -52,165 +52,163 @@ Device (MCHC)
, 11,
DIBR, 20, /* DMIBAR [31:12] */
- Offset (0xa0), /* Top of Used Memory */
- TOM, 64,
-
- Offset (0xa8), /* Top of Upper Used Memory */
- TUUD, 64,
+ Offset (0xa0),
+ TOM, 64, /* Top of Used Memory */
+ TUUD, 64, /* Top of Upper Used Memory */
Offset (0xbc), /* Top of Low Used Memory */
TLUD, 32,
}
}
-Name (MCRS, ResourceTemplate ()
-{
- /* Bus Numbers */
- WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
- 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100)
-
- /* IO Region 0 */
- DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode,
- EntireRange,
- 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8)
-
- /* PCI Config Space */
- Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
-
- /* IO Region 1 */
- DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode,
- EntireRange,
- 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300)
-
- /* VGA memory (0xa0000-0xbffff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
- 0x00020000)
-
- /* OPROM reserved (0xc0000-0xc3fff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
- 0x00004000)
-
- /* OPROM reserved (0xc4000-0xc7fff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
- 0x00004000)
-
- /* OPROM reserved (0xc8000-0xcbfff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
- 0x00004000)
-
- /* OPROM reserved (0xcc000-0xcffff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
- 0x00004000)
-
- /* OPROM reserved (0xd0000-0xd3fff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
- 0x00004000)
-
- /* OPROM reserved (0xd4000-0xd7fff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
- 0x00004000)
-
- /* OPROM reserved (0xd8000-0xdbfff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
- 0x00004000)
-
- /* OPROM reserved (0xdc000-0xdffff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
- 0x00004000)
-
- /* BIOS Extension (0xe0000-0xe3fff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
- 0x00004000)
-
- /* BIOS Extension (0xe4000-0xe7fff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
- 0x00004000)
-
- /* BIOS Extension (0xe8000-0xebfff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
- 0x00004000)
-
- /* BIOS Extension (0xec000-0xeffff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000ec000, 0x000effff, 0x00000000,
- 0x00004000)
-
- /* System BIOS (0xf0000-0xfffff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
- 0x00010000)
-
- /* PCI Memory Region (TLUD - 0xdfffffff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- NonCacheable, ReadWrite,
- 0x00000000, 0x00000000, 0xdfffffff, 0x00000000,
- 0xE0000000,,, PM01)
-
- /* PCI Memory Region (TUUD - (TUUD + ABOVE_4G_MMIO_SIZE)) */
- QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- NonCacheable, ReadWrite,
- 0x00000000, 0x10000, 0x1ffff, 0x00000000,
- 0x10000,,, PM02)
-
- /* PCH reserved resource (0xfc800000-0xfe7fffff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, PCH_PRESERVED_BASE_ADDRESS, 0xfe7fffff,
- 0x00000000, PCH_PRESERVED_BASE_SIZE)
-
- /* TPM Area (0xfed40000-0xfed47fff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0xfed40000, 0xfed47fff, 0x00000000,
- 0x00008000)
-})
-
Method (_CRS, 0, Serialized)
{
+ Name (MCRS, ResourceTemplate ()
+ {
+ /* Bus Numbers */
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100)
+
+ /* IO Region 0 */
+ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ EntireRange,
+ 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8)
+
+ /* PCI Config Space */
+ Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
+
+ /* IO Region 1 */
+ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ EntireRange,
+ 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300)
+
+ /* VGA memory (0xa0000-0xbffff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
+ 0x00020000)
+
+ /* OPROM reserved (0xc0000-0xc3fff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
+ 0x00004000)
+
+ /* OPROM reserved (0xc4000-0xc7fff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
+ 0x00004000)
+
+ /* OPROM reserved (0xc8000-0xcbfff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
+ 0x00004000)
+
+ /* OPROM reserved (0xcc000-0xcffff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
+ 0x00004000)
+
+ /* OPROM reserved (0xd0000-0xd3fff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
+ 0x00004000)
+
+ /* OPROM reserved (0xd4000-0xd7fff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
+ 0x00004000)
+
+ /* OPROM reserved (0xd8000-0xdbfff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
+ 0x00004000)
+
+ /* OPROM reserved (0xdc000-0xdffff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
+ 0x00004000)
+
+ /* BIOS Extension (0xe0000-0xe3fff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
+ 0x00004000)
+
+ /* BIOS Extension (0xe4000-0xe7fff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
+ 0x00004000)
+
+ /* BIOS Extension (0xe8000-0xebfff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
+ 0x00004000)
+
+ /* BIOS Extension (0xec000-0xeffff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000ec000, 0x000effff, 0x00000000,
+ 0x00004000)
+
+ /* System BIOS (0xf0000-0xfffff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
+ 0x00010000)
+
+ /* PCI Memory Region (TLUD - 0xdfffffff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ NonCacheable, ReadWrite,
+ 0x00000000, 0x00000000, 0xdfffffff, 0x00000000,
+ 0xE0000000,,, PM01)
+
+ /* PCI Memory Region (TUUD - (TUUD + ABOVE_4G_MMIO_SIZE)) */
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ NonCacheable, ReadWrite,
+ 0x00000000, 0x10000, 0x1ffff, 0x00000000,
+ 0x10000,,, PM02)
+
+ /* PCH reserved resource (0xfc800000-0xfe7fffff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, PCH_PRESERVED_BASE_ADDRESS, 0xfe7fffff,
+ 0x00000000, PCH_PRESERVED_BASE_SIZE)
+
+ /* TPM Area (0xfed40000-0xfed47fff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0xfed40000, 0xfed47fff, 0x00000000,
+ 0x00008000)
+ })
+
/* Find PCI resource area in MCRS */
- CreateDwordField (^MCRS, ^PM01._MIN, PMIN)
- CreateDwordField (^MCRS, ^PM01._MAX, PMAX)
- CreateDwordField (^MCRS, ^PM01._LEN, PLEN)
+ CreateDwordField (MCRS, PM01._MIN, PMIN)
+ CreateDwordField (MCRS, PM01._MAX, PMAX)
+ CreateDwordField (MCRS, PM01._LEN, PLEN)
/*
* Fix up PCI memory region
* Start with Top of Lower Usable DRAM
*/
- Store (^MCHC.TLUD, PMIN)
+ Store (\_SB.PCI0.MCHC.TLUD, PMIN)
Add (Subtract (PMAX, PMIN), 1, PLEN)
/* Patch PM02 range based on Memory Size */
- CreateQwordField (^MCRS, ^PM02._MIN, MMIN)
- CreateQwordField (^MCRS, ^PM02._MAX, MMAX)
- CreateQwordField (^MCRS, ^PM02._LEN, MLEN)
+ CreateQwordField (MCRS, PM02._MIN, MMIN)
+ CreateQwordField (MCRS, PM02._MAX, MMAX)
+ CreateQwordField (MCRS, PM02._LEN, MLEN)
- Store (^MCHC.TUUD, Local0)
+ Store (\_SB.PCI0.MCHC.TUUD, Local0)
If (LLessEqual (Local0, BASE_32GB)) {
Store (BASE_32GB, MMIN)
@@ -221,58 +219,42 @@ Method (_CRS, 0, Serialized)
}
Subtract (Add (MMIN, MLEN), 1, MMAX)
- Return (^MCRS)
+ Return (MCRS)
}
-Name (EP_B, 0) /* to store EP BAR */
-Name (MH_B, 0) /* to store MCH BAR */
-Name (PC_B, 0) /* to store PCIe BAR */
-Name (PC_L, 0) /* to store PCIe BAR Length */
-Name (DM_B, 0) /* to store DMI BAR */
-
/* Get MCH BAR */
Method (GMHB, 0, Serialized)
{
- If (LEqual (MH_B, 0)) {
- ShiftLeft (\_SB.PCI0.MCHC.MHBR, 15, MH_B)
- }
- Return (MH_B)
+ ShiftLeft (\_SB.PCI0.MCHC.MHBR, 15, Local0)
+ Return (Local0)
}
/* Get EP BAR */
Method (GEPB, 0, Serialized)
{
- If (LEqual (EP_B, 0)) {
- ShiftLeft (\_SB.PCI0.MCHC.EPBR, 12, EP_B)
- }
- Return (EP_B)
+ ShiftLeft (\_SB.PCI0.MCHC.EPBR, 12, Local0)
+ Return (Local0)
}
/* Get PCIe BAR */
Method (GPCB, 0, Serialized)
{
- If (LEqual (PC_B, 0)) {
- ShiftLeft (\_SB.PCI0.MCHC.PXBR, 26, PC_B)
- }
- Return (PC_B)
+ ShiftLeft (\_SB.PCI0.MCHC.PXBR, 26, Local0)
+ Return (Local0)
}
/* Get PCIe Length */
Method (GPCL, 0, Serialized)
{
- If (LEqual (PC_L, 0)) {
- ShiftRight (0x10000000, \_SB.PCI0.MCHC.PXSZ, PC_L)
- }
- Return (PC_L)
+ ShiftRight (0x10000000, \_SB.PCI0.MCHC.PXSZ, Local0)
+ Return (Local0)
}
/* Get DMI BAR */
Method (GDMB, 0, Serialized)
{
- If (LEqual (DM_B, 0)) {
- ShiftLeft (\_SB.PCI0.MCHC.DIBR, 12, DM_B)
- }
- Return (DM_B)
+ ShiftLeft (\_SB.PCI0.MCHC.DIBR, 12, Local0)
+ Return (Local0)
}
/* PCI Device Resource Consumption */
@@ -281,59 +263,61 @@ Device (PDRC)
Name (_HID, EISAID ("PNP0C02"))
Name (_UID, 1)
- Name (BUF0, ResourceTemplate ()
- {
- /* MCH BAR _BAS will be updated in _CRS below according to
- * B0:D0:F0:Reg.48h
- */
- Memory32Fixed (ReadWrite, 0, 0x08000, MCHB)
-
- /* DMI BAR _BAS will be updated in _CRS below according to
- * B0:D0:F0:Reg.68h
- */
- Memory32Fixed (ReadWrite, 0, 0x01000, DMIB)
-
- /* EP BAR _BAS will be updated in _CRS below according to
- * B0:D0:F0:Reg.40h
- */
- Memory32Fixed (ReadWrite, 0, 0x01000, EGPB)
-
- /* PCI Express BAR _BAS and _LEN will be updated in
- * _CRS below according to B0:D0:F0:Reg.60h
- */
- Memory32Fixed (ReadWrite, 0, 0, PCIX)
-
- /* VTD engine memory range.
- */
- Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE)
-
- /* FLASH range */
- Memory32Fixed (ReadOnly, 0xFF000000, 0x1000000, FIOH)
-
- /* Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) */
- Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000, LIOH)
-
- /* HPET address decode range */
- Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400)
- })
-
Method (_CRS, 0, Serialized)
{
- CreateDwordField (BUF0, ^MCHB._BAS, MBR0)
+ Name (BUF0, ResourceTemplate ()
+ {
+ /* MCH BAR _BAS will be updated in _CRS below according to
+ * B0:D0:F0:Reg.48h
+ */
+ Memory32Fixed (ReadWrite, 0, 0x08000, MCHB)
+
+ /* DMI BAR _BAS will be updated in _CRS below according to
+ * B0:D0:F0:Reg.68h
+ */
+ Memory32Fixed (ReadWrite, 0, 0x01000, DMIB)
+
+ /* EP BAR _BAS will be updated in _CRS below according to
+ * B0:D0:F0:Reg.40h
+ */
+ Memory32Fixed (ReadWrite, 0, 0x01000, EGPB)
+
+ /* PCI Express BAR _BAS and _LEN will be updated in
+ * _CRS below according to B0:D0:F0:Reg.60h
+ */
+ Memory32Fixed (ReadWrite, 0, 0, PCIX)
+
+ /* VTD engine memory range. */
+ Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE)
+
+ /* FLASH range */
+ Memory32Fixed (ReadOnly, 0, CONFIG_ROM_SIZE, FIOH)
+
+ /* Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) */
+ Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000)
+
+ /* HPET address decode range */
+ Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400)
+ })
+
+ CreateDwordField (BUF0, MCHB._BAS, MBR0)
Store (\_SB.PCI0.GMHB (), MBR0)
- CreateDwordField (BUF0, ^DMIB._BAS, DBR0)
+ CreateDwordField (BUF0, DMIB._BAS, DBR0)
Store (\_SB.PCI0.GDMB (), DBR0)
- CreateDwordField (BUF0, ^EGPB._BAS, EBR0)
+ CreateDwordField (BUF0, EGPB._BAS, EBR0)
Store (\_SB.PCI0.GEPB (), EBR0)
- CreateDwordField (BUF0, ^PCIX._BAS, XBR0)
+ CreateDwordField (BUF0, PCIX._BAS, XBR0)
Store (\_SB.PCI0.GPCB (), XBR0)
- CreateDwordField (BUF0, ^PCIX._LEN, XSZ0)
+ CreateDwordField (BUF0, PCIX._LEN, XSZ0)
Store (\_SB.PCI0.GPCL (), XSZ0)
+ CreateDwordField (BUF0, FIOH._BAS, FBR0)
+ Subtract(0x100000000, CONFIG_ROM_SIZE, FBR0)
+
Return (BUF0)
}
}
diff --git a/src/soc/intel/skylake/acpi/systemagent.asl b/src/soc/intel/skylake/acpi/systemagent.asl
index e7b2d90463..589fcc1518 100644
--- a/src/soc/intel/skylake/acpi/systemagent.asl
+++ b/src/soc/intel/skylake/acpi/systemagent.asl
@@ -23,8 +23,6 @@
Name (_HID, EISAID ("PNP0A08")) /* PCIe */
Name (_CID, EISAID ("PNP0A03")) /* PCI */
-Name (_BBN, 0)
-
Device (MCHC)
{
Name (_ADR, 0x00000000)
@@ -55,175 +53,172 @@ Device (MCHC)
Offset (0x70), /* ME Base Address */
MEBA, 64,
-
- Offset (0xa0), /* Top of Used Memory */
- TOM, 64,
-
- Offset (0xa8), /* Top of Upper Used Memory */
- TUUD, 64,
+ Offset (0xa0),
+ TOM, 64, /* Top of Used Memory */
+ TUUD, 64, /* Top of Upper Used Memory */
Offset (0xbc), /* Top of Low Used Memory */
TLUD, 32,
}
}
-Name (MCRS, ResourceTemplate ()
+Method (_CRS, 0, Serialized)
{
- /* Bus Numbers */
- WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
- 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100)
-
- /* IO Region 0 */
- DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode,
- EntireRange,
- 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8)
-
- /* PCI Config Space */
- Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
-
- /* IO Region 1 */
- DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode,
- EntireRange,
- 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300)
-
- /* VGA memory (0xa0000-0xbffff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
- 0x00020000)
-
- /* OPROM reserved (0xc0000-0xc3fff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
- 0x00004000)
-
- /* OPROM reserved (0xc4000-0xc7fff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
- 0x00004000)
-
- /* OPROM reserved (0xc8000-0xcbfff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
- 0x00004000)
-
- /* OPROM reserved (0xcc000-0xcffff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
- 0x00004000)
-
- /* OPROM reserved (0xd0000-0xd3fff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
- 0x00004000)
-
- /* OPROM reserved (0xd4000-0xd7fff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
- 0x00004000)
-
- /* OPROM reserved (0xd8000-0xdbfff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
- 0x00004000)
-
- /* OPROM reserved (0xdc000-0xdffff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
- 0x00004000)
-
- /* BIOS Extension (0xe0000-0xe3fff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
- 0x00004000)
-
- /* BIOS Extension (0xe4000-0xe7fff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
- 0x00004000)
-
- /* BIOS Extension (0xe8000-0xebfff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
- 0x00004000)
-
- /* BIOS Extension (0xec000-0xeffff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000ec000, 0x000effff, 0x00000000,
- 0x00004000)
-
- /* System BIOS (0xf0000-0xfffff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
- 0x00010000)
-
- /* PCI Memory Region (TOLUD - 0xdfffffff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- NonCacheable, ReadWrite,
- 0x00000000, 0x00000000, 0xdfffffff, 0x00000000,
- 0xE0000000,,, PM01)
-
- /* PCI Memory Region (TOUUD - (TOUUD + ABOVE_4G_MMIO_SIZE)) */
- QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- NonCacheable, ReadWrite,
- 0x00000000, 0x10000, 0x1ffff, 0x00000000,
- 0x10000,,, PM02)
-
- /* PCH reserved resource (0xfd000000-0xfe7fffff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0xfd000000, 0xfe7fffff, 0x00000000,
- 0x1800000)
-
- /* TPM Area (0xfed40000-0xfed44fff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
- 0x00005000)
+ Name (MCRS, ResourceTemplate ()
+ {
+ /* Bus Numbers */
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100)
+
+ /* IO Region 0 */
+ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ EntireRange,
+ 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8)
+
+ /* PCI Config Space */
+ Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
+
+ /* IO Region 1 */
+ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ EntireRange,
+ 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300)
+
+ /* VGA memory (0xa0000-0xbffff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
+ 0x00020000)
+
+ /* OPROM reserved (0xc0000-0xc3fff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
+ 0x00004000)
+
+ /* OPROM reserved (0xc4000-0xc7fff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
+ 0x00004000)
+
+ /* OPROM reserved (0xc8000-0xcbfff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
+ 0x00004000)
+
+ /* OPROM reserved (0xcc000-0xcffff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
+ 0x00004000)
+
+ /* OPROM reserved (0xd0000-0xd3fff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
+ 0x00004000)
+
+ /* OPROM reserved (0xd4000-0xd7fff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
+ 0x00004000)
+
+ /* OPROM reserved (0xd8000-0xdbfff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
+ 0x00004000)
+
+ /* OPROM reserved (0xdc000-0xdffff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
+ 0x00004000)
+
+ /* BIOS Extension (0xe0000-0xe3fff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
+ 0x00004000)
+
+ /* BIOS Extension (0xe4000-0xe7fff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
+ 0x00004000)
+
+ /* BIOS Extension (0xe8000-0xebfff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
+ 0x00004000)
+
+ /* BIOS Extension (0xec000-0xeffff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000ec000, 0x000effff, 0x00000000,
+ 0x00004000)
+
+ /* System BIOS (0xf0000-0xfffff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
+ 0x00010000)
+
+ /* PCI Memory Region (TLUD - 0xdfffffff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ NonCacheable, ReadWrite,
+ 0x00000000, 0x00000000, 0xdfffffff, 0x00000000,
+ 0xE0000000,,, PM01)
+
+ /* PCI Memory Region (TUUD - (TUUD + ABOVE_4G_MMIO_SIZE)) */
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ NonCacheable, ReadWrite,
+ 0x00000000, 0x10000, 0x1ffff, 0x00000000,
+ 0x10000,,, PM02)
+
+ /* PCH reserved resource (0xfc800000-0xfe7fffff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, PCH_PRESERVED_BASE_ADDRESS, 0xfe7fffff,
+ 0x00000000, PCH_PRESERVED_BASE_SIZE)
+
+ /* TPM Area (0xfed40000-0xfed44fff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
+ 0x00005000)
})
-Method (_CRS, 0, Serialized)
-{
/* Find PCI resource area in MCRS */
- CreateDwordField (^MCRS, ^PM01._MIN, PMIN)
- CreateDwordField (^MCRS, ^PM01._MAX, PMAX)
- CreateDwordField (^MCRS, ^PM01._LEN, PLEN)
+ CreateDwordField (MCRS, PM01._MIN, PMIN)
+ CreateDwordField (MCRS, PM01._MAX, PMAX)
+ CreateDwordField (MCRS, PM01._LEN, PLEN)
/*
* Fix up PCI memory region
* Start with Top of Lower Usable DRAM
*/
- Store (^MCHC.TLUD, Local0)
- Store (^MCHC.MEBA, Local1)
+ Store (\_SB.PCI0.MCHC.TLUD, Local0)
+ Store (\_SB.PCI0.MCHC.MEBA, Local1)
/* Check if ME base is equal */
If (LEqual (Local0, Local1)) {
/* Use Top Of Memory instead */
- Store (^MCHC.TOM, Local0)
+ Store (\_SB.PCI0.MCHC.TOM, Local0)
}
Store (Local0, PMIN)
Add (Subtract (PMAX, PMIN), 1, PLEN)
/* Patch PM02 range based on Memory Size */
- CreateQwordField (^MCRS, ^PM02._MIN, MMIN)
- CreateQwordField (^MCRS, ^PM02._MAX, MMAX)
- CreateQwordField (^MCRS, ^PM02._LEN, MLEN)
+ CreateQwordField (MCRS, PM02._MIN, MMIN)
+ CreateQwordField (MCRS, PM02._MAX, MMAX)
+ CreateQwordField (MCRS, PM02._LEN, MLEN)
- Store (^MCHC.TUUD, Local0)
+ Store (\_SB.PCI0.MCHC.TUUD, Local0)
If (LLessEqual (Local0, BASE_32GB)) {
Store (BASE_32GB, MMIN)
@@ -234,58 +229,42 @@ Method (_CRS, 0, Serialized)
}
Subtract (Add (MMIN, MLEN), 1, MMAX)
- Return (^MCRS)
+ Return (MCRS)
}
-Name (EP_B, 0) /* to store EP BAR */
-Name (MH_B, 0) /* to store MCH BAR */
-Name (PC_B, 0) /* to store PCIe BAR */
-Name (PC_L, 0) /* to store PCIe BAR Length */
-Name (DM_B, 0) /* to store DMI BAR */
-
/* Get MCH BAR */
Method (GMHB, 0, Serialized)
{
- If (LEqual (MH_B, 0)) {
- ShiftLeft (\_SB.PCI0.MCHC.MHBR, 15, MH_B)
- }
- Return (MH_B)
+ ShiftLeft (\_SB.PCI0.MCHC.MHBR, 15, Local0)
+ Return (Local0)
}
/* Get EP BAR */
Method (GEPB, 0, Serialized)
{
- If (LEqual (EP_B, 0)) {
- ShiftLeft (\_SB.PCI0.MCHC.EPBR, 12, EP_B)
- }
- Return (EP_B)
+ ShiftLeft (\_SB.PCI0.MCHC.EPBR, 12, Local0)
+ Return (Local0)
}
/* Get PCIe BAR */
Method (GPCB, 0, Serialized)
{
- If (LEqual (PC_B, 0)) {
- ShiftLeft (\_SB.PCI0.MCHC.PXBR, 26, PC_B)
- }
- Return (PC_B)
+ ShiftLeft (\_SB.PCI0.MCHC.PXBR, 26, Local0)
+ Return (Local0)
}
/* Get PCIe Length */
Method (GPCL, 0, Serialized)
{
- If (LEqual (PC_L, 0)) {
- ShiftRight (0x10000000, \_SB.PCI0.MCHC.PXSZ, PC_L)
- }
- Return (PC_L)
+ ShiftRight (0x10000000, \_SB.PCI0.MCHC.PXSZ, Local0)
+ Return (Local0)
}
/* Get DMI BAR */
Method (GDMB, 0, Serialized)
{
- If (LEqual (DM_B, 0)) {
- ShiftLeft (\_SB.PCI0.MCHC.DIBR, 12, DM_B)
- }
- Return (DM_B)
+ ShiftLeft (\_SB.PCI0.MCHC.DIBR, 12, Local0)
+ Return (Local0)
}
/* PCI Device Resource Consumption */
@@ -294,70 +273,71 @@ Device (PDRC)
Name (_HID, EISAID ("PNP0C02"))
Name (_UID, 1)
- Name (BUF0, ResourceTemplate ()
- {
- /* MCH BAR _BAS will be updated in _CRS below according to
- * B0:D0:F0:Reg.48h
- */
- Memory32Fixed (ReadWrite, 0, 0x08000, MCHB)
-
- /* DMI BAR _BAS will be updated in _CRS below according to
- * B0:D0:F0:Reg.68h
- */
- Memory32Fixed (ReadWrite, 0, 0x01000, DMIB)
-
- /* EP BAR _BAS will be updated in _CRS below according to
- * B0:D0:F0:Reg.40h
- */
- Memory32Fixed (ReadWrite, 0, 0x01000, EGPB)
-
- /* PCI Express BAR _BAS and _LEN will be updated in
- * _CRS below according to B0:D0:F0:Reg.60h
- */
- Memory32Fixed (ReadWrite, 0, 0, PCIX)
-
- /* MISC ICH TTT base address reserved for the
- * TxT module use.
- */
- Memory32Fixed (ReadWrite, 0xFED20000, 0x20000)
-
- /* VTD engine memory range.
- * Check if the hard code meets the real configuration.
- */
- Memory32Fixed (ReadOnly, 0xFED90000, 0x00004000)
-
- /* MISC ICH. Check if the hard code meets the
- * real configuration.
- */
- Memory32Fixed (ReadWrite, 0xFED45000, 0x4B000, TPMM)
-
- /* FLASH range */
- Memory32Fixed (ReadOnly, 0xFF000000, 0x1000000, FIOH) /* 16MB */
-
- /* Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) */
- Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000, LIOH)
-
- /* HPET address decode range */
- Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400)
- })
-
Method (_CRS, 0, Serialized)
{
- CreateDwordField (BUF0, ^MCHB._BAS, MBR0)
+ Name (BUF0, ResourceTemplate ()
+ {
+ /* MCH BAR _BAS will be updated in _CRS below according to
+ * B0:D0:F0:Reg.48h
+ */
+ Memory32Fixed (ReadWrite, 0, 0x08000, MCHB)
+
+ /* DMI BAR _BAS will be updated in _CRS below according to
+ * B0:D0:F0:Reg.68h
+ */
+ Memory32Fixed (ReadWrite, 0, 0x01000, DMIB)
+
+ /* EP BAR _BAS will be updated in _CRS below according to
+ * B0:D0:F0:Reg.40h
+ */
+ Memory32Fixed (ReadWrite, 0, 0x01000, EGPB)
+
+ /* PCI Express BAR _BAS and _LEN will be updated in
+ * _CRS below according to B0:D0:F0:Reg.60h
+ */
+ Memory32Fixed (ReadWrite, 0, 0, PCIX)
+
+ /* MISC ICH TTT base address reserved for the
+ * TxT module use.
+ */
+ Memory32Fixed (ReadWrite, 0xFED20000, 0x20000)
+
+ /* VTD engine memory range. */
+ Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE)
+
+ /* MISC ICH. Check if the hard code meets the
+ * real configuration.
+ */
+ Memory32Fixed (ReadWrite, 0xFED45000, 0x4B000, TPMM)
+
+ /* FLASH range */
+ Memory32Fixed (ReadOnly, 0, CONFIG_ROM_SIZE, FIOH)
+
+ /* Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) */
+ Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000)
+
+ /* HPET address decode range */
+ Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400)
+ })
+
+ CreateDwordField (BUF0, MCHB._BAS, MBR0)
Store (\_SB.PCI0.GMHB (), MBR0)
- CreateDwordField (BUF0, ^DMIB._BAS, DBR0)
+ CreateDwordField (BUF0, DMIB._BAS, DBR0)
Store (\_SB.PCI0.GDMB (), DBR0)
- CreateDwordField (BUF0, ^EGPB._BAS, EBR0)
+ CreateDwordField (BUF0, EGPB._BAS, EBR0)
Store (\_SB.PCI0.GEPB (), EBR0)
- CreateDwordField (BUF0, ^PCIX._BAS, XBR0)
+ CreateDwordField (BUF0, PCIX._BAS, XBR0)
Store (\_SB.PCI0.GPCB (), XBR0)
- CreateDwordField (BUF0, ^PCIX._LEN, XSZ0)
+ CreateDwordField (BUF0, PCIX._LEN, XSZ0)
Store (\_SB.PCI0.GPCL (), XSZ0)
+ CreateDwordField (BUF0, FIOH._BAS, FBR0)
+ Subtract(0x100000000, CONFIG_ROM_SIZE, FBR0)
+
Return (BUF0)
}
}
diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h
index c73d766953..814dd949d0 100644
--- a/src/soc/intel/skylake/include/soc/iomap.h
+++ b/src/soc/intel/skylake/include/soc/iomap.h
@@ -63,6 +63,9 @@
#define THERMAL_BASE_ADDRESS 0xfe600000
+#define VTD_BASE_ADDRESS 0xFED90000
+#define VTD_BASE_SIZE 0x00004000
+
/* CPU Trace reserved memory size */
#define GDXC_MOT_MEMORY_SIZE (96*MiB)
#define GDXC_IOT_MEMORY_SIZE (32*MiB)
diff --git a/src/soc/intel/tigerlake/acpi/northbridge.asl b/src/soc/intel/tigerlake/acpi/northbridge.asl
index d6c2d346c6..149839d554 100644
--- a/src/soc/intel/tigerlake/acpi/northbridge.asl
+++ b/src/soc/intel/tigerlake/acpi/northbridge.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corp.
+ * Copyright (C) 2019-2020 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -52,11 +52,9 @@ Device (MCHC)
, 11,
DIBR, 20, /* DMIBAR [31:12] */
- Offset (0xa0), /* Top of Used Memory */
- TOM, 64,
-
- Offset (0xa8), /* Top of Upper Used Memory */
- TUUD, 64,
+ Offset (0xa0),
+ TOM, 64, /* Top of Used Memory */
+ TUUD, 64, /* Top of Upper Used Memory */
Offset (0xbc), /* Top of Low Used Memory */
TLUD, 32,
@@ -224,58 +222,39 @@ Method (_CRS, 0, Serialized)
Return (MCRS)
}
-/*
- * TODO: Clean up below functions and follow ASL2.0 code syntax
- */
-Name (EP_B, 0) /* to store EP BAR */
-Name (MH_B, 0) /* to store MCH BAR */
-Name (PC_B, 0) /* to store PCIe BAR */
-Name (PC_L, 0) /* to store PCIe BAR Length */
-Name (DM_B, 0) /* to store DMI BAR */
-
/* Get MCH BAR */
Method (GMHB, 0, Serialized)
{
- If (LEqual (MH_B, 0)) {
- ShiftLeft (\_SB.PCI0.MCHC.MHBR, 15, MH_B)
- }
- Return (MH_B)
+ ShiftLeft (\_SB.PCI0.MCHC.MHBR, 15, Local0)
+ Return (Local0)
}
/* Get EP BAR */
Method (GEPB, 0, Serialized)
{
- If (LEqual (EP_B, 0)) {
- ShiftLeft (\_SB.PCI0.MCHC.EPBR, 12, EP_B)
- }
- Return (EP_B)
+ ShiftLeft (\_SB.PCI0.MCHC.EPBR, 12, Local0)
+ Return (Local0)
}
/* Get PCIe BAR */
Method (GPCB, 0, Serialized)
{
- If (LEqual (PC_B, 0)) {
- ShiftLeft (\_SB.PCI0.MCHC.PXBR, 26, PC_B)
- }
- Return (PC_B)
+ ShiftLeft (\_SB.PCI0.MCHC.PXBR, 26, Local0)
+ Return (Local0)
}
/* Get PCIe Length */
Method (GPCL, 0, Serialized)
{
- If (LEqual (PC_L, 0)) {
- ShiftRight (0x10000000, \_SB.PCI0.MCHC.PXSZ, PC_L)
- }
- Return (PC_L)
+ ShiftRight (0x10000000, \_SB.PCI0.MCHC.PXSZ, Local0)
+ Return (Local0)
}
/* Get DMI BAR */
Method (GDMB, 0, Serialized)
{
- If (LEqual (DM_B, 0)) {
- ShiftLeft (\_SB.PCI0.MCHC.DIBR, 12, DM_B)
- }
- Return (DM_B)
+ ShiftLeft (\_SB.PCI0.MCHC.DIBR, 12, Local0)
+ Return (Local0)
}
/* PCI Device Resource Consumption */
@@ -284,59 +263,61 @@ Device (PDRC)
Name (_HID, EISAID ("PNP0C02"))
Name (_UID, 1)
- Name (BUF0, ResourceTemplate ()
- {
- /* MCH BAR _BAS will be updated in _CRS below according to
- * B0:D0:F0:Reg.48h
- */
- Memory32Fixed (ReadWrite, 0, 0x08000, MCHB)
-
- /* DMI BAR _BAS will be updated in _CRS below according to
- * B0:D0:F0:Reg.68h
- */
- Memory32Fixed (ReadWrite, 0, 0x01000, DMIB)
-
- /* EP BAR _BAS will be updated in _CRS below according to
- * B0:D0:F0:Reg.40h
- */
- Memory32Fixed (ReadWrite, 0, 0x01000, EGPB)
-
- /* PCI Express BAR _BAS and _LEN will be updated in
- * _CRS below according to B0:D0:F0:Reg.60h
- */
- Memory32Fixed (ReadWrite, 0, 0, PCIX)
-
- /* VTD engine memory range.
- */
- Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE)
-
- /* Memory mapped SPI Flash range */
- Memory32Fixed (ReadOnly, 0xFFF00000, 0x1000000)
-
- /* Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) */
- Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000)
-
- /* HPET address decode range */
- Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400)
- })
-
Method (_CRS, 0, Serialized)
{
- CreateDwordField (BUF0, ^MCHB._BAS, MBR0)
+ Name (BUF0, ResourceTemplate ()
+ {
+ /* MCH BAR _BAS will be updated in _CRS below according to
+ * B0:D0:F0:Reg.48h
+ */
+ Memory32Fixed (ReadWrite, 0, 0x08000, MCHB)
+
+ /* DMI BAR _BAS will be updated in _CRS below according to
+ * B0:D0:F0:Reg.68h
+ */
+ Memory32Fixed (ReadWrite, 0, 0x01000, DMIB)
+
+ /* EP BAR _BAS will be updated in _CRS below according to
+ * B0:D0:F0:Reg.40h
+ */
+ Memory32Fixed (ReadWrite, 0, 0x01000, EGPB)
+
+ /* PCI Express BAR _BAS and _LEN will be updated in
+ * _CRS below according to B0:D0:F0:Reg.60h
+ */
+ Memory32Fixed (ReadWrite, 0, 0, PCIX)
+
+ /* VTD engine memory range. */
+ Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE)
+
+ /* FLASH range */
+ Memory32Fixed (ReadOnly, 0, CONFIG_ROM_SIZE, FIOH)
+
+ /* Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) */
+ Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000)
+
+ /* HPET address decode range */
+ Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400)
+ })
+
+ CreateDwordField (BUF0, MCHB._BAS, MBR0)
Store (\_SB.PCI0.GMHB (), MBR0)
- CreateDwordField (BUF0, ^DMIB._BAS, DBR0)
+ CreateDwordField (BUF0, DMIB._BAS, DBR0)
Store (\_SB.PCI0.GDMB (), DBR0)
- CreateDwordField (BUF0, ^EGPB._BAS, EBR0)
+ CreateDwordField (BUF0, EGPB._BAS, EBR0)
Store (\_SB.PCI0.GEPB (), EBR0)
- CreateDwordField (BUF0, ^PCIX._BAS, XBR0)
+ CreateDwordField (BUF0, PCIX._BAS, XBR0)
Store (\_SB.PCI0.GPCB (), XBR0)
- CreateDwordField (BUF0, ^PCIX._LEN, XSZ0)
+ CreateDwordField (BUF0, PCIX._LEN, XSZ0)
Store (\_SB.PCI0.GPCL (), XSZ0)
+ CreateDwordField (BUF0, FIOH._BAS, FBR0)
+ Subtract(0x100000000, CONFIG_ROM_SIZE, FBR0)
+
Return (BUF0)
}
}