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-rw-r--r--src/mainboard/google/dragonegg/dsdt.asl2
-rw-r--r--src/mainboard/google/drallion/dsdt.asl2
-rw-r--r--src/mainboard/google/hatch/dsdt.asl2
-rw-r--r--src/mainboard/google/sarien/dsdt.asl2
-rw-r--r--src/mainboard/intel/cannonlake_rvp/dsdt.asl2
-rw-r--r--src/mainboard/intel/coffeelake_rvp/dsdt.asl2
-rw-r--r--src/mainboard/intel/icelake_rvp/dsdt.asl2
-rw-r--r--src/soc/intel/cannonlake/acpi/globalnvs.asl56
-rw-r--r--src/soc/intel/cannonlake/include/soc/nvs.h30
-rw-r--r--src/soc/intel/common/block/acpi/acpi/globalnvs.asl (renamed from src/soc/intel/icelake/acpi/globalnvs.asl)3
-rw-r--r--src/soc/intel/common/block/include/intelblocks/nvs.h48
-rw-r--r--src/soc/intel/icelake/include/soc/nvs.h30
12 files changed, 58 insertions, 123 deletions
diff --git a/src/mainboard/google/dragonegg/dsdt.asl b/src/mainboard/google/dragonegg/dsdt.asl
index d5c709ec1d..4318dc35f3 100644
--- a/src/mainboard/google/dragonegg/dsdt.asl
+++ b/src/mainboard/google/dragonegg/dsdt.asl
@@ -30,7 +30,7 @@ DefinitionBlock(
#include <soc/intel/icelake/acpi/platform.asl>
// global NVS and variables
- #include <soc/intel/icelake/acpi/globalnvs.asl>
+ #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
// CPU
#include <cpu/intel/common/acpi/cpu.asl>
diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl
index 91d3704276..0a092cff0f 100644
--- a/src/mainboard/google/drallion/dsdt.asl
+++ b/src/mainboard/google/drallion/dsdt.asl
@@ -29,7 +29,7 @@ DefinitionBlock(
#include <soc/intel/cannonlake/acpi/platform.asl>
/* global NVS and variables */
- #include <soc/intel/cannonlake/acpi/globalnvs.asl>
+ #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
/* CPU */
#include <cpu/intel/common/acpi/cpu.asl>
diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl
index 9329b58a79..62478293f3 100644
--- a/src/mainboard/google/hatch/dsdt.asl
+++ b/src/mainboard/google/hatch/dsdt.asl
@@ -30,7 +30,7 @@ DefinitionBlock(
#include <soc/intel/cannonlake/acpi/platform.asl>
/* global NVS and variables */
- #include <soc/intel/cannonlake/acpi/globalnvs.asl>
+ #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
/* CPU */
#include <cpu/intel/common/acpi/cpu.asl>
diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl
index 743a2f0a56..9a5c787a25 100644
--- a/src/mainboard/google/sarien/dsdt.asl
+++ b/src/mainboard/google/sarien/dsdt.asl
@@ -29,7 +29,7 @@ DefinitionBlock(
#include <soc/intel/cannonlake/acpi/platform.asl>
/* global NVS and variables */
- #include <soc/intel/cannonlake/acpi/globalnvs.asl>
+ #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
/* CPU */
#include <cpu/intel/common/acpi/cpu.asl>
diff --git a/src/mainboard/intel/cannonlake_rvp/dsdt.asl b/src/mainboard/intel/cannonlake_rvp/dsdt.asl
index acc4c7c7c3..9a519c0b39 100644
--- a/src/mainboard/intel/cannonlake_rvp/dsdt.asl
+++ b/src/mainboard/intel/cannonlake_rvp/dsdt.asl
@@ -29,7 +29,7 @@ DefinitionBlock(
#include <soc/intel/cannonlake/acpi/platform.asl>
// global NVS and variables
- #include <soc/intel/cannonlake/acpi/globalnvs.asl>
+ #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
Scope (\_SB) {
Device (PCI0)
diff --git a/src/mainboard/intel/coffeelake_rvp/dsdt.asl b/src/mainboard/intel/coffeelake_rvp/dsdt.asl
index f830035318..1d7216aecc 100644
--- a/src/mainboard/intel/coffeelake_rvp/dsdt.asl
+++ b/src/mainboard/intel/coffeelake_rvp/dsdt.asl
@@ -29,7 +29,7 @@ DefinitionBlock(
#include <soc/intel/cannonlake/acpi/platform.asl>
// global NVS and variables
- #include <soc/intel/cannonlake/acpi/globalnvs.asl>
+ #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
Scope (\_SB) {
Device (PCI0)
diff --git a/src/mainboard/intel/icelake_rvp/dsdt.asl b/src/mainboard/intel/icelake_rvp/dsdt.asl
index 6657a6ed6e..152f038fc6 100644
--- a/src/mainboard/intel/icelake_rvp/dsdt.asl
+++ b/src/mainboard/intel/icelake_rvp/dsdt.asl
@@ -30,7 +30,7 @@ DefinitionBlock(
#include <soc/intel/icelake/acpi/platform.asl>
// global NVS and variables
- #include <soc/intel/icelake/acpi/globalnvs.asl>
+ #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
// CPU
#include <cpu/intel/common/acpi/cpu.asl>
diff --git a/src/soc/intel/cannonlake/acpi/globalnvs.asl b/src/soc/intel/cannonlake/acpi/globalnvs.asl
deleted file mode 100644
index 940cf4396b..0000000000
--- a/src/soc/intel/cannonlake/acpi/globalnvs.asl
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* Global Variables */
-
-Name (\PICM, 0) // IOAPIC/8259
-
-/*
- * Global ACPI memory region. This region is used for passing information
- * between coreboot (aka "the system bios"), ACPI, and the SMI handler.
- * Since we don't know where this will end up in memory at ACPI compile time,
- * we have to fix it up in coreboot's ACPI creation phase.
- */
-
-External (NVSA)
-
-OperationRegion (GNVS, SystemMemory, NVSA, 0x2000)
-Field (GNVS, ByteAcc, NoLock, Preserve)
-{
- /* Miscellaneous */
- OSYS, 16, // 0x00 - Operating System
- SMIF, 8, // 0x02 - SMI function
- PCNT, 8, // 0x03 - Processor Count
- PPCM, 8, // 0x04 - Max PPC State
- TLVL, 8, // 0x05 - Throttle Level Limit
- LIDS, 8, // 0x06 - LID State
- PWRS, 8, // 0x07 - AC Power State
- CBMC, 32, // 0x08 - 0x0b AC Power State
- PM1I, 64, // 0x0c - 0x13 PM1 wake status bit
- GPEI, 64, // 0x14 - 0x17 GPE wake status bit
- DPTE, 8, // 0x1c - Enable DPTF
- NHLA, 64, // 0x1d - 0x24 NHLT Address
- NHLL, 32, // 0x25 - 0x28 NHLT Length
- CID1, 16, // 0x29 - 0x2a Wifi Country Identifier
- U2WE, 16, // 0x2b - 0x2c USB2 Wake Enable Bitmap
- U3WE, 16, // 0x2d - 0x2e USB3 Wake Enable Bitmap
- UIOR, 8, // 0x2f - UART debug controller init on S3 resume
-
- /* ChromeOS specific */
- Offset (0x100),
- #include <vendorcode/google/chromeos/acpi/gnvs.asl>
-}
diff --git a/src/soc/intel/cannonlake/include/soc/nvs.h b/src/soc/intel/cannonlake/include/soc/nvs.h
index 1cb22faa74..3bd7bc2bca 100644
--- a/src/soc/intel/cannonlake/include/soc/nvs.h
+++ b/src/soc/intel/cannonlake/include/soc/nvs.h
@@ -18,34 +18,6 @@
#ifndef _SOC_NVS_H_
#define _SOC_NVS_H_
-#include <commonlib/helpers.h>
-#include <vendorcode/google/chromeos/gnvs.h>
-
-typedef struct global_nvs_t {
- /* Miscellaneous */
- u16 osys; /* 0x00 - 0x01 Operating System */
- u8 smif; /* 0x02 - SMI function call ("TRAP") */
- u8 pcnt; /* 0x03 - Processor Count */
- u8 ppcm; /* 0x04 - Max PPC State */
- u8 tlvl; /* 0x05 - Throttle Level Limit */
- u8 lids; /* 0x06 - LID State */
- u8 pwrs; /* 0x07 - AC Power State */
- u32 cbmc; /* 0x08 - 0xb AC Power State */
- u64 pm1i; /* 0x0c - 0x13 PM1 wake status bit */
- u64 gpei; /* 0x14 - 0x1b GPE wake status bit */
- u8 dpte; /* 0x1c - Enable DPTF */
- u64 nhla; /* 0x1d - 0x24 NHLT Address */
- u32 nhll; /* 0x25 - 0x28 NHLT Length */
- u16 cid1; /* 0x29 - 0x2a Wifi Country Identifier */
- u16 u2we; /* 0x2b - 0x2c USB2 Wake Enable Bitmap */
- u16 u3we; /* 0x2d - 0x2e USB3 Wake Enable Bitmap */
- u8 uior; /* 0x2f - UART debug controller init on S3 resume */
- u8 unused[208];
-
- /* ChromeOS specific (0x100 - 0xfff) */
- chromeos_acpi_t chromeos;
-} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
-
+#include <intelblocks/nvs.h>
#endif
diff --git a/src/soc/intel/icelake/acpi/globalnvs.asl b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl
index 678ce5ac23..8e8241bc78 100644
--- a/src/soc/intel/icelake/acpi/globalnvs.asl
+++ b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2018 Intel Corp.
+ * Copyright (C) 2019 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -30,7 +30,6 @@ OperationRegion (GNVS, SystemMemory, NVSA, 0x2000)
Field (GNVS, ByteAcc, NoLock, Preserve)
{
/* Miscellaneous */
- Offset (0x00),
OSYS, 16, // 0x00 - Operating System
SMIF, 8, // 0x02 - SMI function
PCNT, 8, // 0x03 - Processor Count
diff --git a/src/soc/intel/common/block/include/intelblocks/nvs.h b/src/soc/intel/common/block/include/intelblocks/nvs.h
new file mode 100644
index 0000000000..5f367b68b3
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/nvs.h
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_INTEL_COMMON_BLOCK_NVS_H
+#define SOC_INTEL_COMMON_BLOCK_NVS_H
+
+#include <commonlib/helpers.h>
+#include <vendorcode/google/chromeos/gnvs.h>
+
+typedef struct global_nvs_t {
+ /* Miscellaneous */
+ u16 osys; /* 0x00 - 0x01 Operating System */
+ u8 smif; /* 0x02 - SMI function call ("TRAP") */
+ u8 pcnt; /* 0x03 - Processor Count */
+ u8 ppcm; /* 0x04 - Max PPC State */
+ u8 tlvl; /* 0x05 - Throttle Level Limit */
+ u8 lids; /* 0x06 - LID State */
+ u8 pwrs; /* 0x07 - AC Power State */
+ u32 cbmc; /* 0x08 - 0xb AC Power State */
+ u64 pm1i; /* 0x0c - 0x13 PM1 wake status bit */
+ u64 gpei; /* 0x14 - 0x1b GPE wake status bit */
+ u8 dpte; /* 0x1c - Enable DPTF */
+ u64 nhla; /* 0x1d - 0x24 NHLT Address */
+ u32 nhll; /* 0x25 - 0x28 NHLT Length */
+ u16 cid1; /* 0x29 - 0x2a Wifi Country Identifier */
+ u16 u2we; /* 0x2b - 0x2c USB2 Wake Enable Bitmap */
+ u16 u3we; /* 0x2d - 0x2e USB3 Wake Enable Bitmap */
+ u8 uior; /* 0x2f - UART debug controller init on S3 resume */
+ u8 unused[208];
+
+ /* ChromeOS specific (0x100 - 0xfff) */
+ chromeos_acpi_t chromeos;
+} __packed global_nvs_t;
+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
+
+#endif
diff --git a/src/soc/intel/icelake/include/soc/nvs.h b/src/soc/intel/icelake/include/soc/nvs.h
index b2d903a4f5..c855df0305 100644
--- a/src/soc/intel/icelake/include/soc/nvs.h
+++ b/src/soc/intel/icelake/include/soc/nvs.h
@@ -16,34 +16,6 @@
#ifndef _SOC_NVS_H_
#define _SOC_NVS_H_
-#include <commonlib/helpers.h>
-#include <vendorcode/google/chromeos/gnvs.h>
-
-typedef struct global_nvs_t {
- /* Miscellaneous */
- u16 osys; /* 0x00 - 0x01 Operating System */
- u8 smif; /* 0x02 - SMI function call ("TRAP") */
- u8 pcnt; /* 0x03 - Processor Count */
- u8 ppcm; /* 0x04 - Max PPC State */
- u8 tlvl; /* 0x05 - Throttle Level Limit */
- u8 lids; /* 0x06 - LID State */
- u8 pwrs; /* 0x07 - AC Power State */
- u32 cbmc; /* 0x08 - 0xb AC Power State */
- u64 pm1i; /* 0x0c - 0x13 PM1 wake status bit */
- u64 gpei; /* 0x14 - 0x1b GPE wake status bit */
- u8 dpte; /* 0x1c - Enable DPTF */
- u64 nhla; /* 0x1d - 0x24 NHLT Address */
- u32 nhll; /* 0x25 - 0x28 NHLT Length */
- u16 cid1; /* 0x29 - 0x2a Wifi Country Identifier */
- u16 u2we; /* 0x2b - 0x2c USB2 Wake Enable Bitmap */
- u16 u3we; /* 0x2d - 0x2e USB3 Wake Enable Bitmap */
- u8 uior; /* 0x2f - UART debug controller init on S3 resume */
- u8 unused[208];
-
- /* ChromeOS specific (0x100 - 0xfff) */
- chromeos_acpi_t chromeos;
-} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
-
+#include <intelblocks/nvs.h>
#endif