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-rw-r--r--src/soc/mediatek/common/rtc.c9
-rw-r--r--src/soc/mediatek/mt8183/include/soc/rtc.h25
-rw-r--r--src/soc/mediatek/mt8183/rtc.c25
3 files changed, 33 insertions, 26 deletions
diff --git a/src/soc/mediatek/common/rtc.c b/src/soc/mediatek/common/rtc.c
index a9142b612d..fe252b5d64 100644
--- a/src/soc/mediatek/common/rtc.c
+++ b/src/soc/mediatek/common/rtc.c
@@ -91,12 +91,15 @@ int rtc_xosc_write(u16 val)
u16 bbpu;
rtc_write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK1);
- udelay(200);
+ if (!rtc_busy_wait())
+ return 0;
rtc_write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK2);
- udelay(200);
+ if (!rtc_busy_wait())
+ return 0;
rtc_write(RTC_OSC32CON, val);
- udelay(200);
+ if (!rtc_busy_wait())
+ return 0;
rtc_read(RTC_BBPU, &bbpu);
bbpu |= RTC_BBPU_KEY | RTC_BBPU_RELOAD;
diff --git a/src/soc/mediatek/mt8183/include/soc/rtc.h b/src/soc/mediatek/mt8183/include/soc/rtc.h
index 3d115fec41..841a202519 100644
--- a/src/soc/mediatek/mt8183/include/soc/rtc.h
+++ b/src/soc/mediatek/mt8183/include/soc/rtc.h
@@ -100,18 +100,25 @@ enum {
};
enum {
- RTC_EMBCK_SRC_SEL = 1 << 8,
- RTC_EMBCK_SEL_MODE = 3 << 6,
- RTC_XOSC32_ENB = 1 << 5,
- RTC_REG_XOSC32_ENB = 1 << 15
+ RTC_XOSCCALI_MASK = 0x1F << 0,
+ RTC_XOSC32_ENB = 1U << 5,
+ RTC_EMB_HW_MODE = 0U << 6,
+ RTC_EMB_K_EOSC32_MODE = 1U << 6,
+ RTC_EMB_SW_DCXO_MODE = 2U << 6,
+ RTC_EMB_SW_EOSC32_MODE = 3U << 6,
+ RTC_EMBCK_SEL_MODE_MASK = 3U << 6,
+ RTC_EMBCK_SRC_SEL = 1U << 8,
+ RTC_EMBCK_SEL_OPTION = 1U << 9,
+ RTC_GPS_CKOUT_EN = 1U << 10,
+ RTC_REG_XOSC32_ENB = 1U << 15
};
enum {
- RTC_LPD_OPT_XOSC_AND_EOSC_LPD = 0 << 13,
- RTC_LPD_OPT_EOSC_LPD = 1 << 13,
- RTC_LPD_OPT_XOSC_LPD = 2 << 13,
- RTC_LPD_OPT_F32K_CK_ALIVE = 3 << 13,
- RTC_LPD_OPT_MASK = 3 << 13
+ RTC_LPD_OPT_XOSC_AND_EOSC_LPD = 0U << 13,
+ RTC_LPD_OPT_EOSC_LPD = 1U << 13,
+ RTC_LPD_OPT_XOSC_LPD = 2U << 13,
+ RTC_LPD_OPT_F32K_CK_ALIVE = 3U << 13,
+ RTC_LPD_OPT_MASK = 3U << 13
};
/* PMIC TOP Register Definition */
diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c
index 62256ebc1b..5879088434 100644
--- a/src/soc/mediatek/mt8183/rtc.c
+++ b/src/soc/mediatek/mt8183/rtc.c
@@ -33,20 +33,19 @@ static int rtc_enable_dcxo(void)
mdelay(1);
if (!rtc_writeif_unlock()) { /* Unlock for reload */
- rtc_info("rtc_writeif_unlock() fail\n");
+ rtc_info("rtc_writeif_unlock() failed\n");
return 0;
}
rtc_read(RTC_OSC32CON, &osc32con);
- osc32con &= ~RTC_EMBCK_SRC_SEL;
- osc32con |= RTC_XOSC32_ENB | RTC_REG_XOSC32_ENB;
+ osc32con &= ~(RTC_EMBCK_SRC_SEL | RTC_EMBCK_SEL_MODE_MASK
+ | RTC_GPS_CKOUT_EN);
+ osc32con |= RTC_XOSC32_ENB | RTC_REG_XOSC32_ENB
+ | RTC_EMB_K_EOSC32_MODE | RTC_EMBCK_SEL_OPTION;
if (!rtc_xosc_write(osc32con)) {
- rtc_info("rtc_xosc_write() fail\n");
+ rtc_info("rtc_xosc_write() failed\n");
return 0;
}
- rtc_read(RTC_BBPU, &bbpu);
- rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
- rtc_write_trigger();
rtc_read(RTC_CON, &con);
rtc_read(RTC_OSC32CON, &osc32con);
@@ -197,12 +196,6 @@ int rtc_init(u8 recover)
goto err;
}
- /* using dcxo 32K clock */
- if (!rtc_enable_dcxo()) {
- ret = -RTC_STATUS_OSC_SETTING_FAIL;
- goto err;
- }
-
if (recover)
mdelay(20);
@@ -264,7 +257,7 @@ void poweroff(void)
u16 bbpu;
if (!rtc_writeif_unlock())
- rtc_info("rtc_writeif_unlock() fail\n");
+ rtc_info("rtc_writeif_unlock() failed\n");
/* pull PWRBB low */
bbpu = RTC_BBPU_KEY | RTC_BBPU_RELOAD | RTC_BBPU_PWREN;
rtc_write(RTC_BBPU, bbpu);
@@ -311,6 +304,10 @@ void rtc_boot(void)
pwrap_write_field(PMIC_RG_DCXO_CW02, 0xF, 0xF, 0);
pwrap_write_field(PMIC_RG_SCK_TOP_CON0, 0x1, 0x1, 0);
+ /* use dcxo 32K clock */
+ if (!rtc_enable_dcxo())
+ rtc_info("rtc_enable_dcxo() failed\n");
+
rtc_boot_common();
rtc_bbpu_power_on();
}