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-rw-r--r--src/mainboard/google/volteer/variants/baseboard/devicetree.cb7
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb6
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb6
-rw-r--r--src/soc/intel/tigerlake/chip.h3
-rw-r--r--src/soc/intel/tigerlake/romstage/fsp_params.c3
5 files changed, 0 insertions, 25 deletions
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index 8a6bcf394e..28931e486d 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -121,13 +121,6 @@ chip soc/intel/tigerlake
register "PchHdaAudioLinkDmicEnable[1]" = "1"
register "PchHdaAudioLinkSspEnable[0]" = "1"
register "PchHdaAudioLinkSspEnable[1]" = "1"
- # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T
- register "PchHdaIDispLinkTmode" = "2"
- # iDisp-Link Freq 4: 96MHz, 3: 48MHz.
- register "PchHdaIDispLinkFrequency" = "4"
- # Not disconnected/enumerable
- register "PchHdaIDispCodecDisconnect" = "0"
-
# TCSS USB3
register "TcssXhciEn" = "1"
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index 8b4f8f8bbf..82f358e8b6 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -121,12 +121,6 @@ chip soc/intel/tigerlake
register "PchHdaAudioLinkSspEnable[1]" = "0"
register "PchHdaAudioLinkSspEnable[2]" = "1"
register "PchHdaAudioLinkSndwEnable[0]" = "1"
- # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T
- register "PchHdaIDispLinkTmode" = "2"
- # iDisp-Link Freq 4: 96MHz, 3: 48MHz.
- register "PchHdaIDispLinkFrequency" = "4"
- # Not disconnected/enumerable
- register "PchHdaIDispCodecDisconnect" = "0"
# Intel Common SoC Config
register "common_soc_config" = "{
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index 9b5774bd1c..fec2fefa16 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -117,12 +117,6 @@ chip soc/intel/tigerlake
register "PchHdaAudioLinkSspEnable[1]" = "0"
register "PchHdaAudioLinkSspEnable[2]" = "1"
register "PchHdaAudioLinkSndwEnable[0]" = "1"
- # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T
- register "PchHdaIDispLinkTmode" = "2"
- # iDisp-Link Freq 4: 96MHz, 3: 48MHz.
- register "PchHdaIDispLinkFrequency" = "4"
- # Not disconnected/enumerable
- register "PchHdaIDispCodecDisconnect" = "0"
# Intel Common SoC Config
register "common_soc_config" = "{
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 26eab4c8fd..a3319d4ee4 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -96,9 +96,6 @@ struct soc_intel_tigerlake_config {
uint8_t PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS];
uint8_t PchHdaAudioLinkSspEnable[MAX_HD_AUDIO_SSP_LINKS];
uint8_t PchHdaAudioLinkSndwEnable[MAX_HD_AUDIO_SNDW_LINKS];
- uint8_t PchHdaIDispLinkTmode;
- uint8_t PchHdaIDispLinkFrequency;
- uint8_t PchHdaIDispCodecDisconnect;
/* PCIe Root Ports */
uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c
index 6056b4b0c1..b4521e2a61 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params.c
@@ -165,9 +165,6 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
sizeof(m_cfg->PchHdaAudioLinkSspEnable));
memcpy(m_cfg->PchHdaAudioLinkSndwEnable, config->PchHdaAudioLinkSndwEnable,
sizeof(m_cfg->PchHdaAudioLinkSndwEnable));
- m_cfg->PchHdaIDispLinkTmode = config->PchHdaIDispLinkTmode;
- m_cfg->PchHdaIDispLinkFrequency = config->PchHdaIDispLinkFrequency;
- m_cfg->PchHdaIDispCodecDisconnect = config->PchHdaIDispCodecDisconnect;
/* Vt-D config */
m_cfg->VtdDisable = 0;