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-rw-r--r--src/cpu/amd/car/post_cache_as_ram.c6
-rw-r--r--src/include/cpu/amd/car.h15
-rw-r--r--src/include/lib.h8
-rw-r--r--src/mainboard/amd/dinar/romstage.c3
-rw-r--r--src/mainboard/amd/inagua/romstage.c1
-rw-r--r--src/mainboard/amd/olivehill/romstage.c3
-rw-r--r--src/mainboard/amd/parmer/romstage.c3
-rw-r--r--src/mainboard/amd/persimmon/romstage.c3
-rw-r--r--src/mainboard/amd/south_station/romstage.c1
-rw-r--r--src/mainboard/amd/thatcher/romstage.c3
-rw-r--r--src/mainboard/amd/torpedo/romstage.c2
-rw-r--r--src/mainboard/amd/union_station/romstage.c1
-rw-r--r--src/mainboard/asrock/e350m1/romstage.c2
-rw-r--r--src/mainboard/asrock/imb-a180/romstage.c3
-rw-r--r--src/mainboard/asus/f2a85-m/romstage.c4
-rw-r--r--src/mainboard/digitallogic/msm800sev/romstage.c2
-rwxr-xr-xsrc/mainboard/gizmosphere/gizmo/romstage.c3
-rw-r--r--src/mainboard/hp/pavilion_m6_1035dx/romstage.c5
-rw-r--r--src/mainboard/jetway/nf81-t56n-lf/romstage.c4
-rw-r--r--src/mainboard/lippert/frontrunner-af/romstage.c3
-rw-r--r--src/mainboard/lippert/toucan-af/romstage.c3
-rw-r--r--src/mainboard/pcengines/alix1c/romstage.c2
-rw-r--r--src/mainboard/pcengines/alix2d/romstage.c2
-rw-r--r--src/mainboard/supermicro/h8qgi/romstage.c2
-rw-r--r--src/mainboard/supermicro/h8scm/romstage.c2
-rw-r--r--src/mainboard/tyan/s8226/romstage.c2
26 files changed, 39 insertions, 49 deletions
diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index 97127855be..51caec59ea 100644
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -5,6 +5,7 @@
#include <arch/stages.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
+#include <cpu/amd/car.h>
#include "cbmem.h"
#include "cpu/amd/car/disable_cache_as_ram.c"
@@ -75,8 +76,6 @@ static void vErrata343(void)
#endif
}
-void cache_as_ram_switch_stack(void *resume_backup_memory);
-
void post_cache_as_ram(void)
{
void *resume_backup_memory = NULL;
@@ -113,9 +112,6 @@ void post_cache_as_ram(void)
}
void
-cache_as_ram_new_stack (void *resume_backup_memory);
-
-void
cache_as_ram_new_stack (void *resume_backup_memory __attribute__ ((unused)))
{
/* We can put data to stack again */
diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h
new file mode 100644
index 0000000000..a001c9345f
--- /dev/null
+++ b/src/include/cpu/amd/car.h
@@ -0,0 +1,15 @@
+#ifndef _CPU_AMD_CAR_H
+#define _CPU_AMD_CAR_H
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
+void done_cache_as_ram_main(void);
+void post_cache_as_ram(void);
+
+void cache_as_ram_switch_stack(void *resume_backup_memory);
+void cache_as_ram_new_stack(void *resume_backup_memory);
+
+#if CONFIG_CPU_AMD_AGESA
+void disable_cache_as_ram(void);
+#endif
+
+#endif
diff --git a/src/include/lib.h b/src/include/lib.h
index db2e9c776e..c272eb57b5 100644
--- a/src/include/lib.h
+++ b/src/include/lib.h
@@ -50,14 +50,6 @@ int checkstack(void *top_of_stack, int core);
extern unsigned char _estack[];
#endif
-/* Defined in romstage.c */
-#if CONFIG_CPU_AMD_GEODE_LX
-void cache_as_ram_main(void);
-#else
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
-#endif
-void post_cache_as_ram(void);
-
/* Defined in src/lib/hexdump.c */
void hexdump(const void *memory, size_t length);
void hexdump32(char LEVEL, const void *d, int len);
diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c
index 91b385f6fc..776ecd5e2e 100644
--- a/src/mainboard/amd/dinar/romstage.c
+++ b/src/mainboard/amd/dinar/romstage.c
@@ -27,6 +27,7 @@
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <console/loglevel.h>
+#include "cpu/amd/car.h"
#include "cpu/x86/bist.h"
#include "superio/smsc/sch4037/sch4037_early_init.c"
#include "superio/smsc/sio1036/sio1036_early_init.c"
@@ -40,8 +41,6 @@
#define SERIAL_DEV PNP_DEV(CONFIG_SIO_PORT, SMSCSUPERIO_SP1)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
-void disable_cache_as_ram(void);
u32 agesawrapper_amdinitmmio (void);
u32 agesawrapper_amdinitreset (void);
diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c
index 718d2b2c2f..98c74d6d03 100644
--- a/src/mainboard/amd/inagua/romstage.c
+++ b/src/mainboard/amd/inagua/romstage.c
@@ -30,6 +30,7 @@
#include <console/console.h>
#include <console/loglevel.h>
#include <cpu/x86/mtrr.h>
+#include "cpu/amd/car.h"
#include "agesawrapper.h"
#include "cpu/x86/bist.h"
#include "superio/smsc/kbc1100/kbc1100_early_init.c"
diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c
index 9431d4a9a9..6422393f6a 100644
--- a/src/mainboard/amd/olivehill/romstage.c
+++ b/src/mainboard/amd/olivehill/romstage.c
@@ -28,6 +28,7 @@
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <console/loglevel.h>
+#include "cpu/amd/car.h"
#include "agesawrapper.h"
#include "cpu/x86/bist.h"
#include "cpu/x86/lapic.h"
@@ -37,8 +38,6 @@
#include "src/drivers/pc80/i8259.c"
#include "cbmem.h"
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
-void disable_cache_as_ram(void);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c
index 202442c029..a5d041fc80 100644
--- a/src/mainboard/amd/parmer/romstage.c
+++ b/src/mainboard/amd/parmer/romstage.c
@@ -28,6 +28,7 @@
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <console/loglevel.h>
+#include "cpu/amd/car.h"
#include "agesawrapper.h"
#include "cpu/x86/bist.h"
#include "cpu/x86/lapic.h"
@@ -37,8 +38,6 @@
#include "src/drivers/pc80/i8259.c"
#include "cbmem.h"
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
-void disable_cache_as_ram(void);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index 81804a93ff..47c03ec54a 100644
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -29,6 +29,7 @@
#include <console/console.h>
#include <console/loglevel.h>
#include <cpu/x86/mtrr.h>
+#include "cpu/amd/car.h"
#include "agesawrapper.h"
#include "cpu/x86/bist.h"
#include <superio/fintek/common/fintek.h>
@@ -43,8 +44,6 @@
#include "cpu/amd/mtrr.h"
#include "cpu/amd/agesa/s3_resume.h"
-void disable_cache_as_ram(void); /* cache_as_ram.inc */
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1)
diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c
index 5e70ecc8ed..be340aa9ac 100644
--- a/src/mainboard/amd/south_station/romstage.c
+++ b/src/mainboard/amd/south_station/romstage.c
@@ -30,6 +30,7 @@
#include <console/console.h>
#include <console/loglevel.h>
#include <cpu/x86/mtrr.h>
+#include "cpu/amd/car.h"
#include "agesawrapper.h"
#include "cpu/x86/bist.h"
#include <superio/fintek/common/fintek.h>
diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c
index 6bf8ac62eb..9c3cf5bf64 100644
--- a/src/mainboard/amd/thatcher/romstage.c
+++ b/src/mainboard/amd/thatcher/romstage.c
@@ -28,6 +28,7 @@
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <console/loglevel.h>
+#include "cpu/amd/car.h"
#include "agesawrapper.h"
#include "cpu/x86/bist.h"
#include "cpu/x86/lapic.h"
@@ -40,8 +41,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, LPC47N217_SP1)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
-void disable_cache_as_ram(void);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c
index f6204b9000..58b88d0f61 100644
--- a/src/mainboard/amd/torpedo/romstage.c
+++ b/src/mainboard/amd/torpedo/romstage.c
@@ -27,6 +27,7 @@
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <console/loglevel.h>
+#include "cpu/amd/car.h"
#include "agesawrapper.h"
#include "cpu/x86/bist.h"
#include "superio/smsc/kbc1100/kbc1100_early_init.c"
@@ -38,7 +39,6 @@
#include <arch/cpu.h>
#include "platform_cfg.h"
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c
index 68687553f4..0a7ef7c4b0 100644
--- a/src/mainboard/amd/union_station/romstage.c
+++ b/src/mainboard/amd/union_station/romstage.c
@@ -30,6 +30,7 @@
#include <console/console.h>
#include <console/loglevel.h>
#include <cpu/x86/mtrr.h>
+#include "cpu/amd/car.h"
#include "agesawrapper.h"
#include "cpu/x86/bist.h"
#include "cpu/x86/lapic.h"
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index bf850a30c8..cbfa7434d3 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -29,6 +29,7 @@
#include <console/console.h>
#include <console/loglevel.h>
#include <cpu/x86/mtrr.h>
+#include "cpu/amd/car.h"
#include "agesawrapper.h"
#include "cpu/x86/bist.h"
#include "superio/winbond/w83627hf/early_serial.c"
@@ -38,7 +39,6 @@
#include <sb_cimx.h>
#include "SBPLATFORM.h"
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
#define SERIAL_DEV PNP_DEV(CONFIG_SIO_PORT, W83627HF_SP1)
diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c
index 9b069b77ce..59d95f9e0f 100644
--- a/src/mainboard/asrock/imb-a180/romstage.c
+++ b/src/mainboard/asrock/imb-a180/romstage.c
@@ -28,6 +28,7 @@
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <console/loglevel.h>
+#include "cpu/amd/car.h"
#include "agesawrapper.h"
#include "cpu/x86/bist.h"
#include "cpu/x86/lapic.h"
@@ -40,8 +41,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627UHG_SP1)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
-void disable_cache_as_ram(void);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c
index ee9983d88f..4aa4b04e4a 100644
--- a/src/mainboard/asus/f2a85-m/romstage.c
+++ b/src/mainboard/asus/f2a85-m/romstage.c
@@ -26,6 +26,7 @@
#include <cbmem.h>
#include <console/console.h>
#include <cpu/amd/agesa/s3_resume.h>
+#include "cpu/amd/car.h"
#include <cpu/x86/bist.h>
#include <cpu/x86/lapic.h>
#include <device/pci_def.h>
@@ -40,9 +41,6 @@
#include <drivers/pc80/i8259.c>
#include <superio/ite/it8712f/early_serial.c>
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
-void disable_cache_as_ram(void);
-
#define MMIO_NON_POSTED_START 0xfed00000
#define MMIO_NON_POSTED_END 0xfedfffff
#define SB_MMIO 0xFED80000
diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c
index cc2fc4bbe0..b96f8ae27e 100644
--- a/src/mainboard/digitallogic/msm800sev/romstage.c
+++ b/src/mainboard/digitallogic/msm800sev/romstage.c
@@ -8,6 +8,7 @@
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include <cpu/amd/lxdef.h>
+#include <cpu/amd/car.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include <spd.h>
#include "southbridge/amd/cs5536/early_smbus.c"
@@ -75,6 +76,5 @@ void main(unsigned long bist)
/* we are finding the return does not work on this board. Explicitly call the label that is
* after the call to us. This is gross, but sometimes at this level it is the only way out
*/
- void done_cache_as_ram_main(void);
done_cache_as_ram_main();
}
diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c
index 705d42938d..f639d1f56c 100755
--- a/src/mainboard/gizmosphere/gizmo/romstage.c
+++ b/src/mainboard/gizmosphere/gizmo/romstage.c
@@ -30,6 +30,7 @@
#include <console/console.h>
#include <console/loglevel.h>
#include <cpu/x86/mtrr.h>
+#include "cpu/amd/car.h"
#include "agesawrapper.h"
#include "cpu/x86/bist.h"
#include "drivers/pc80/i8254.c"
@@ -45,8 +46,6 @@
#define MSR_MTRR_VARIABLE_MASK6 0x020D
#define MSR_PSTATE_CONTROL 0xC0010062
-void disable_cache_as_ram(void); /* cache_as_ram.inc */
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c
index dd19679adc..24751f45f5 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c
@@ -27,6 +27,7 @@
#include <cpu/amd/agesa/s3_resume.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/lapic.h>
+#include <cpu/amd/car.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <stdint.h>
@@ -36,10 +37,6 @@
#include "src/drivers/pc80/i8254.c"
#include "src/drivers/pc80/i8259.c"
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
-void disable_cache_as_ram(void);
-
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
index 3e962d3274..848faf725f 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
@@ -38,6 +38,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/amd/mtrr.h>
+#include <cpu/amd/car.h>
#include <sb_cimx.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
#include <superio/fintek/common/fintek.h>
@@ -47,9 +48,6 @@
#include "drivers/pc80/i8254.c"
#include "drivers/pc80/i8259.c"
-void disable_cache_as_ram(void); /* cache_as_ram.inc */
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
-
/* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */
#define SERIAL_DEV PNP_DEV(0x2e, F71869AD_SP1)
diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c
index 9ecd0872bc..16fb8ab21b 100644
--- a/src/mainboard/lippert/frontrunner-af/romstage.c
+++ b/src/mainboard/lippert/frontrunner-af/romstage.c
@@ -29,6 +29,7 @@
#include <console/console.h>
#include <console/loglevel.h>
#include <cpu/x86/mtrr.h>
+#include "cpu/amd/car.h"
#include "agesawrapper.h"
#include "cpu/x86/bist.h"
#include "superio/smsc/smscsuperio/early_serial.c"
@@ -42,8 +43,6 @@
#include "cpu/amd/mtrr.h"
#include "cpu/amd/agesa/s3_resume.h"
-void disable_cache_as_ram(void); /* cache_as_ram.inc */
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c
index 4f62268e0e..9f8cf1ade3 100644
--- a/src/mainboard/lippert/toucan-af/romstage.c
+++ b/src/mainboard/lippert/toucan-af/romstage.c
@@ -29,6 +29,7 @@
#include <console/console.h>
#include <console/loglevel.h>
#include <cpu/x86/mtrr.h>
+#include "cpu/amd/car.h"
#include "agesawrapper.h"
#include "cpu/x86/bist.h"
#include "superio/winbond/w83627dhg/w83627dhg.h"
@@ -42,8 +43,6 @@
#include "cpu/amd/mtrr.h"
#include "cpu/amd/agesa/s3_resume.h"
-void disable_cache_as_ram(void); /* cache_as_ram.inc */
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
#define SERIAL_DEV PNP_DEV(0x4e, W83627DHG_SP1)
diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c
index c3f964df83..1c4ae095c9 100644
--- a/src/mainboard/pcengines/alix1c/romstage.c
+++ b/src/mainboard/pcengines/alix1c/romstage.c
@@ -29,6 +29,7 @@
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include <cpu/amd/lxdef.h>
+#include <cpu/amd/car.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include "northbridge/amd/lx/raminit.h"
@@ -162,6 +163,5 @@ void main(unsigned long bist)
* call the label that is after the call to us. This is gross, but
* sometimes at this level it is the only way out.
*/
- void done_cache_as_ram_main(void);
done_cache_as_ram_main();
}
diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c
index 6946900e2a..18453acdf2 100644
--- a/src/mainboard/pcengines/alix2d/romstage.c
+++ b/src/mainboard/pcengines/alix2d/romstage.c
@@ -29,6 +29,7 @@
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include <cpu/amd/lxdef.h>
+#include <cpu/amd/car.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include "northbridge/amd/lx/raminit.h"
@@ -186,6 +187,5 @@ void main(unsigned long bist)
* call the label that is after the call to us. This is gross, but
* sometimes at this level it is the only way out.
*/
- void done_cache_as_ram_main(void);
done_cache_as_ram_main();
}
diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c
index ea4ed8eeff..acb05ab665 100644
--- a/src/mainboard/supermicro/h8qgi/romstage.c
+++ b/src/mainboard/supermicro/h8qgi/romstage.c
@@ -26,6 +26,7 @@
#include <arch/stages.h>
#include "cpu/x86/bist.h"
#include "cpu/x86/lapic.h"
+#include "cpu/amd/car.h"
#include "agesawrapper.h"
#include "northbridge/amd/agesa/family10/reset_test.h"
#include <nb_cimx.h>
@@ -33,7 +34,6 @@
#include "superio/nuvoton/wpcm450/wpcm450.h"
#include "superio/winbond/w83627dhg/w83627dhg.h"
-extern void disable_cache_as_ram(void); /* cache_as_ram.inc */
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c
index 9ee1dfa694..8801c45c8e 100644
--- a/src/mainboard/supermicro/h8scm/romstage.c
+++ b/src/mainboard/supermicro/h8scm/romstage.c
@@ -26,6 +26,7 @@
#include <arch/stages.h>
#include "cpu/x86/bist.h"
#include "cpu/x86/lapic.h"
+#include "cpu/amd/car.h"
#include "agesawrapper.h"
#include "northbridge/amd/agesa/family10/reset_test.h"
#include <nb_cimx.h>
@@ -35,7 +36,6 @@
#include "superio/nuvoton/wpcm450/wpcm450.h"
#include "superio/winbond/w83627dhg/w83627dhg.h"
-extern void disable_cache_as_ram(void); /* cache_as_ram.inc */
#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
#define DUMMY_DEV PNP_DEV(0x2e, 0)
diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c
index a6c33e81a3..49361a80ce 100644
--- a/src/mainboard/tyan/s8226/romstage.c
+++ b/src/mainboard/tyan/s8226/romstage.c
@@ -26,6 +26,7 @@
#include <arch/stages.h>
#include "cpu/x86/bist.h"
#include "cpu/x86/lapic.h"
+#include "cpu/amd/car.h"
#include "agesawrapper.h"
#include "northbridge/amd/agesa/family10/reset_test.h"
#include <nb_cimx.h>
@@ -35,7 +36,6 @@
#include "src/drivers/pc80/i8254.c"
#include "src/drivers/pc80/i8259.c"
-extern void disable_cache_as_ram(void); /* cache_as_ram.inc */
#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
#define DUMMY_DEV PNP_DEV(0x2e, 0)