diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/fsp_baytrail/chip.h | 10 | ||||
| -rw-r--r-- | src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 2 | ||||
| -rw-r--r-- | src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h | 4 |
3 files changed, 15 insertions, 1 deletions
diff --git a/src/soc/intel/fsp_baytrail/chip.h b/src/soc/intel/fsp_baytrail/chip.h index 8a88d44174..35dafa9af1 100644 --- a/src/soc/intel/fsp_baytrail/chip.h +++ b/src/soc/intel/fsp_baytrail/chip.h @@ -217,6 +217,16 @@ struct soc_intel_fsp_baytrail_config { #define ENABLE_IGD_DISABLE UPD_DISABLE #define ENABLE_IGD_ENABLE UPD_ENABLE + /* AutoSelfRefreshEnable */ + uint8_t AutoSelfRefreshEnable; + #define AUTO_SELF_REFRESH_DEFAULT UPD_DEFAULT + #define AUTO_SELF_REFRESH_DISABLE UPD_DISABLE + #define AUTO_SELF_REFRESH_ENABLE UPD_ENABLE + + /* APTaskTimeoutCnt */ + uint16_t APTaskTimeoutCnt; + #define AP_TASK_TIMEOUT_CNT_DEFAULT UPD_DEFAULT + /* Memory down data */ uint8_t EnableMemoryDown; #define MEMORY_DOWN_DEFAULT UPD_DEFAULT diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index 1327533d46..107bfad569 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -113,6 +113,8 @@ static void ConfigureDefaultUpdData(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *U UPD_DEFAULT_CHECK(PcdEMMC45HS200Enabled); UPD_DEFAULT_CHECK(PcdEMMC45RetuneTimerValue); UPD_DEFAULT_CHECK(PcdEnableIgd); + UPD_DEFAULT_CHECK(AutoSelfRefreshEnable); + UPD_DEFAULT_CHECK(APTaskTimeoutCnt); if ((config->PcdeMMCBootMode != EMMC_USE_DEFAULT) || (config->PcdeMMCBootMode != EMMC_FOLLOWS_DEVICETREE)) diff --git a/src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h b/src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h index 76f7ce7b8a..4bdcb79b72 100644 --- a/src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h +++ b/src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h @@ -102,7 +102,9 @@ typedef struct _UPD_DATA_REGION { UINT8 PcdEMMC45HS200Enabled; /* Offset 0x0052 */ UINT8 PcdEMMC45RetuneTimerValue; /* Offset 0x0053 */ UINT8 PcdEnableIgd; /* Offset 0x0054 */ - UINT8 UnusedUpdSpace1[155]; /* Offset 0x0055 */ + UINT8 AutoSelfRefreshEnable; /* Offset 0x0055 */ + UINT16 APTaskTimeoutCnt; /* Offset 0x0056 */ + UINT8 UnusedUpdSpace1[152]; /* Offset 0x0058 */ MEMORY_DOWN_DATA PcdMemoryParameters; /* Offset 0x00F0 */ UINT16 PcdRegionTerminator; /* Offset 0x0100 */ } UPD_DATA_REGION; |