7 files changed, 64 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c
index c122d2a1c7..0e974ba53d 100644
--- a/src/southbridge/intel/bd82x6x/azalia.c
+++ b/src/southbridge/intel/bd82x6x/azalia.c
@@ -331,6 +331,11 @@ static void azalia_init(struct device *dev)
 	pci_write_config8(dev, 0x43, reg8);
 }
 
+static const char *azalia_acpi_name(device_t dev)
+{
+	return "HDEF";
+}
+
 static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
 	if (!vendor || !device) {
@@ -353,6 +358,7 @@ static struct device_operations azalia_ops = {
 	.init			= azalia_init,
 	.scan_bus		= 0,
 	.ops_pci		= &azalia_pci_ops,
+	.acpi_name		= azalia_acpi_name,
 };
 
 static const unsigned short pci_device_ids[] = { 0x1c20, 0x1e20, 0 };
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index c9fee89062..209c8edd65 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -814,6 +814,11 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	fadt->x_gpe1_blk.addrh = 0x0;
 }
 
+static const char *lpc_acpi_name(device_t dev)
+{
+	return "LPCB";
+}
+
 static void southbridge_fill_ssdt(device_t device)
 {
 	device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
@@ -841,6 +846,7 @@ static struct device_operations device_ops = {
 	.write_acpi_tables      = acpi_write_hpet,
 	.acpi_inject_dsdt_generator = southbridge_inject_dsdt,
 	.acpi_fill_ssdt_generator = southbridge_fill_ssdt,
+	.acpi_name		= lpc_acpi_name,
 	.init			= lpc_init,
 	.final			= lpc_final,
 	.enable			= pch_lpc_enable,
diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c
index 91add02d7c..a3eaba963f 100644
--- a/src/southbridge/intel/bd82x6x/pcie.c
+++ b/src/southbridge/intel/bd82x6x/pcie.c
@@ -20,6 +20,7 @@
 #include <device/pciexp.h>
 #include <device/pci_ids.h>
 #include <southbridge/intel/common/pciehp.h>
+#include <assert.h>
 #include "pch.h"
 
 static void pch_pcie_pm_early(struct device *dev)
@@ -284,6 +285,26 @@ static void pch_pciexp_scan_bridge(device_t dev)
 	pch_pcie_pm_late(dev);
 }
 
+static const char *pch_pcie_acpi_name(device_t dev)
+{
+	ASSERT(dev);
+
+	if (PCI_SLOT(dev->path.pci.devfn) == 0x1c) {
+		static const char *names[] = { "RP01",
+				"RP02",
+				"RP03",
+				"RP04",
+				"RP05",
+				"RP06",
+				"RP07",
+				"RP08"};
+
+		return names[PCI_FUNC(dev->path.pci.devfn)];
+	}
+
+	return NULL;
+}
+
 static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
 	/* NOTE: This is not the default position! */
@@ -307,6 +328,7 @@ static struct device_operations device_ops = {
 	.init			= pci_init,
 	.enable			= pch_pcie_enable,
 	.scan_bus		= pch_pciexp_scan_bridge,
+	.acpi_name		= pch_pcie_acpi_name,
 	.ops_pci		= &pci_ops,
 };
 
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c
index d217a0448d..ac4945d011 100644
--- a/src/southbridge/intel/bd82x6x/sata.c
+++ b/src/southbridge/intel/bd82x6x/sata.c
@@ -244,6 +244,11 @@ static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 	}
 }
 
+static const char *sata_acpi_name(device_t dev)
+{
+	return "SATA";
+}
+
 static void sata_fill_ssdt(device_t dev)
 {
 	config_t *config = dev->chip_info;
@@ -264,6 +269,7 @@ static struct device_operations sata_ops = {
 	.enable			= sata_enable,
 	.scan_bus		= 0,
 	.ops_pci		= &sata_pci_ops,
+	.acpi_name		= sata_acpi_name,
 };
 
 static const unsigned short pci_device_ids[] = { 0x1c00, 0x1c01, 0x1c02, 0x1c03,
diff --git a/src/southbridge/intel/bd82x6x/smbus.c b/src/southbridge/intel/bd82x6x/smbus.c
index 5778e255b7..c450d9b555 100644
--- a/src/southbridge/intel/bd82x6x/smbus.c
+++ b/src/southbridge/intel/bd82x6x/smbus.c
@@ -143,6 +143,11 @@ static void smbus_read_resources(device_t dev)
 	res = pci_get_resource(dev, PCI_BASE_ADDRESS_0);
 }
 
+static const char *smbus_acpi_name(device_t dev)
+{
+	return "SBUS";
+}
+
 static struct device_operations smbus_ops = {
 	.read_resources		= smbus_read_resources,
 	.set_resources		= pci_dev_set_resources,
@@ -151,6 +156,7 @@ static struct device_operations smbus_ops = {
 	.init			= pch_smbus_init,
 	.ops_smbus_bus		= &lops_smbus_bus,
 	.ops_pci		= &smbus_pci_ops,
+	.acpi_name		= smbus_acpi_name,
 };
 
 static const unsigned short pci_device_ids[] = { 0x1c22, 0x1e22, 0 };
diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c
index 2712a5b158..42d7a83d98 100644
--- a/src/southbridge/intel/bd82x6x/usb_ehci.c
+++ b/src/southbridge/intel/bd82x6x/usb_ehci.c
@@ -94,6 +94,17 @@ static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned devic
 	pci_write_config8(dev, 0x80, access_cntl);
 }
 
+static const char *usb_ehci_acpi_name(device_t dev)
+{
+	switch (dev->path.pci.devfn) {
+	case PCI_DEVFN(0x1a, 0):
+		return "EHC2";
+	case PCI_DEVFN(0x1d, 0):
+		return "EHC1";
+	}
+	return NULL;
+}
+
 static struct pci_operations lops_pci = {
 	.set_subsystem	= &usb_ehci_set_subsystem,
 };
@@ -105,6 +116,7 @@ static struct device_operations usb_ehci_ops = {
 	.init			= usb_ehci_init,
 	.scan_bus		= 0,
 	.ops_pci		= &lops_pci,
+	.acpi_name		= usb_ehci_acpi_name,
 };
 
 static const unsigned short pci_device_ids[] = { 0x1c26, 0x1c2d, 0x1e26, 0x1e2d,
diff --git a/src/southbridge/intel/bd82x6x/usb_xhci.c b/src/southbridge/intel/bd82x6x/usb_xhci.c
index 74deb522a6..1aeb8643b3 100644
--- a/src/southbridge/intel/bd82x6x/usb_xhci.c
+++ b/src/southbridge/intel/bd82x6x/usb_xhci.c
@@ -51,6 +51,11 @@ static void usb_xhci_init(struct device *dev)
 	printk(BIOS_DEBUG, "done.\n");
 }
 
+static const char *xhci_acpi_name(device_t dev)
+{
+	return "XHC";
+}
+
 static void xhci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
 	if (!vendor || !device) {
@@ -73,6 +78,7 @@ static struct device_operations usb_xhci_ops = {
 	.init			= usb_xhci_init,
 	.scan_bus		= 0,
 	.ops_pci		= &xhci_pci_ops,
+	.acpi_name		= xhci_acpi_name,
 };
 
 static const unsigned short pci_device_ids[] = { 0x1e31, 0 };