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-rw-r--r--src/Kconfig29
-rw-r--r--src/cpu/amd/agesa/Kconfig1
2 files changed, 17 insertions, 13 deletions
diff --git a/src/Kconfig b/src/Kconfig
index 25bb450174..b78b162e9d 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -274,18 +274,28 @@ config RELOCATABLE_RAMSTAGE
wake. When selecting this option the romstage is responsible for
determing a stack location to use for loading the ramstage.
+choice
+ prompt "Stage Cache for ACPI S3 resume"
+ default NO_STAGE_CACHE if !HAVE_ACPI_RESUME || !RELOCATABLE_RAMSTAGE
+ default TSEG_STAGE_CACHE if SMM_TSEG
+
+config NO_STAGE_CACHE
+ bool "Disabled"
+ help
+ Do not save any component in stage cache for resume path. On resume,
+ all components would be read back from CBFS again.
+
config TSEG_STAGE_CACHE
- bool
- default y
- depends on !NO_STAGE_CACHE && SMM_TSEG
+ bool "TSEG"
+ depends on SMM_TSEG
help
The option enables stage cache support for platform. Platform
can stash copies of postcar, ramstage and raw runtime data
inside SMM TSEG, to be restored on S3 resume path.
config CBMEM_STAGE_CACHE
- bool "Cache stages in CBMEM"
- depends on !NO_STAGE_CACHE && !TSEG_STAGE_CACHE
+ bool "CBMEM"
+ depends on !SMM_TSEG
help
The option enables stage cache support for platform. Platform
can stash copies of postcar, ramstage and raw runtime data
@@ -297,6 +307,8 @@ config CBMEM_STAGE_CACHE
If unsure, select 'N'
+endchoice
+
config UPDATE_IMAGE
bool "Update existing coreboot.rom image"
help
@@ -1153,13 +1165,6 @@ config RELOCATABLE_MODULES
building relocatable modules in the RAM stage. Those modules can be
loaded anywhere and all the relocations are handled automatically.
-config NO_STAGE_CACHE
- bool
- default y if !HAVE_ACPI_RESUME || !RELOCATABLE_RAMSTAGE
- help
- Do not save any component in stage cache for resume path. On resume,
- all components would be read back from CBFS again.
-
config GENERIC_GPIO_LIB
bool
help
diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig
index 2c8f9c5e37..fae2565a47 100644
--- a/src/cpu/amd/agesa/Kconfig
+++ b/src/cpu/amd/agesa/Kconfig
@@ -26,7 +26,6 @@ config CPU_AMD_AGESA
select UDELAY_LAPIC
select LAPIC_MONOTONIC_TIMER
select SPI_FLASH if HAVE_ACPI_RESUME
- select CBMEM_STAGE_CACHE if HAVE_ACPI_RESUME
select SMM_ASEG
select NO_FIXED_XIP_ROM_SIZE
select SSE2