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-rw-r--r--src/mainboard/apple/macbookair4_2/romstage.c4
-rw-r--r--src/mainboard/compulab/intense_pc/romstage.c6
-rw-r--r--src/mainboard/gigabyte/ga-b75m-d3h/romstage.c1
-rw-r--r--src/mainboard/google/butterfly/romstage.c7
-rw-r--r--src/mainboard/google/link/romstage.c16
-rw-r--r--src/mainboard/google/parrot/romstage.c6
-rw-r--r--src/mainboard/google/stout/romstage.c3
-rw-r--r--src/mainboard/hp/2570p/devicetree.cb1
-rw-r--r--src/mainboard/hp/2570p/romstage.c2
-rw-r--r--src/mainboard/hp/2760p/devicetree.cb1
-rw-r--r--src/mainboard/hp/2760p/romstage.c2
-rw-r--r--src/mainboard/hp/8460p/devicetree.cb1
-rw-r--r--src/mainboard/hp/8460p/romstage.c2
-rw-r--r--src/mainboard/hp/8470p/devicetree.cb1
-rw-r--r--src/mainboard/hp/8470p/romstage.c2
-rw-r--r--src/mainboard/hp/8770w/devicetree.cb1
-rw-r--r--src/mainboard/hp/8770w/romstage.c2
-rw-r--r--src/mainboard/hp/folio_9470m/devicetree.cb1
-rw-r--r--src/mainboard/hp/folio_9470m/romstage.c2
-rw-r--r--src/mainboard/hp/revolve_810_g1/devicetree.cb1
-rw-r--r--src/mainboard/hp/revolve_810_g1/romstage.c2
-rw-r--r--src/mainboard/intel/emeraldlake2/devicetree.cb5
-rw-r--r--src/mainboard/intel/emeraldlake2/romstage.c6
-rw-r--r--src/mainboard/lenovo/l520/romstage.c4
-rw-r--r--src/mainboard/lenovo/s230u/romstage.c3
-rw-r--r--src/mainboard/lenovo/t420/romstage.c4
-rw-r--r--src/mainboard/lenovo/t420s/romstage.c4
-rw-r--r--src/mainboard/lenovo/t430/romstage.c3
-rw-r--r--src/mainboard/lenovo/t430s/romstage.c4
-rw-r--r--src/mainboard/lenovo/t520/romstage.c4
-rw-r--r--src/mainboard/lenovo/t530/romstage.c4
-rw-r--r--src/mainboard/lenovo/x131e/romstage.c5
-rw-r--r--src/mainboard/lenovo/x1_carbon_gen1/romstage.c4
-rw-r--r--src/mainboard/lenovo/x220/romstage.c4
-rw-r--r--src/mainboard/lenovo/x230/romstage.c4
-rw-r--r--src/mainboard/samsung/lumpy/devicetree.cb1
-rw-r--r--src/mainboard/samsung/lumpy/romstage.c3
-rw-r--r--src/mainboard/samsung/stumpy/devicetree.cb1
-rw-r--r--src/mainboard/samsung/stumpy/romstage.c3
-rw-r--r--src/mainboard/sapphire/pureplatinumh61/romstage.c4
-rw-r--r--src/southbridge/intel/bd82x6x/early_pch.c22
41 files changed, 35 insertions, 121 deletions
diff --git a/src/mainboard/apple/macbookair4_2/romstage.c b/src/mainboard/apple/macbookair4_2/romstage.c
index 6fee17ab0c..d04582d1ed 100644
--- a/src/mainboard/apple/macbookair4_2/romstage.c
+++ b/src/mainboard/apple/macbookair4_2/romstage.c
@@ -23,10 +23,6 @@
void pch_enable_lpc(void)
{
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0681);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c1641);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x001c0301);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00fc0701);
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0070);
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x80000000);
}
diff --git a/src/mainboard/compulab/intense_pc/romstage.c b/src/mainboard/compulab/intense_pc/romstage.c
index 6d0b3af8c0..6c3d980b65 100644
--- a/src/mainboard/compulab/intense_pc/romstage.c
+++ b/src/mainboard/compulab/intense_pc/romstage.c
@@ -33,12 +33,6 @@ void pch_enable_lpc(void)
u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN;
pci_write_config16(dev, LPC_EN, lpc_config);
- /* Map 1 byte to the LPC bus. */
- pci_write_config32(dev, LPC_GEN1_DEC, 0x00164d);
-
- /* Map a range for the runtime_port registers to the LPC bus. */
- pci_write_config32(dev, LPC_GEN2_DEC, 0xc0181);
-
#if CONFIG(DRIVERS_UART_8250IO)
/* Enable COM1 */
if (sio1007_enable_uart_at(SIO_PORT)) {
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
index 67bcbcb8c9..b35a8b4af9 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
@@ -30,7 +30,6 @@ void pch_enable_lpc(void)
pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN |
CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01);
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c
index d34b1e4574..844f754cfc 100644
--- a/src/mainboard/google/butterfly/romstage.c
+++ b/src/mainboard/google/butterfly/romstage.c
@@ -33,13 +33,6 @@ void pch_enable_lpc(void)
/* EC Decode Range Port60/64 and Port62/66 */
/* Enable EC and PS/2 Keyboard/Mouse*/
pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN);
-
- /* EC Decode Range Port68/6C */
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (0x68 & ~3) | 0x40001);
-
- /* EC Decode Range Port 380-387 */
- pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0x380 | 0x40001);
-
}
void mainboard_rcba_config(void)
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index 8da13080b3..2f3f07cdce 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -34,28 +34,12 @@
void pch_enable_lpc(void)
{
- const struct device *lpc;
- const struct southbridge_intel_bd82x6x_config *config = NULL;
-
- lpc = pcidev_on_root(0x1f, 0);
- if (!lpc)
- return;
- if (lpc->chip_info)
- config = lpc->chip_info;
- if (!config)
- return;
-
/* Set COM1/COM2 decode range */
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
/* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */
pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | \
GAMEL_LPC_EN | COMA_LPC_EN);
-
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec);
}
void mainboard_rcba_config(void)
diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c
index 76a4b4b677..ac06fbc83e 100644
--- a/src/mainboard/google/parrot/romstage.c
+++ b/src/mainboard/google/parrot/romstage.c
@@ -31,12 +31,6 @@ void pch_enable_lpc(void)
/* Parrot EC Decode Range Port60/64, Port62/66 */
/* Enable EC, PS/2 Keyboard/Mouse */
pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN);
-
- /* Map EC_IO decode to the LPC bus */
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (EC_IO & ~3) | 0x00040001);
-
- /* Map EC registers 68/6C decode to the LPC bus */
- pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, (68 & ~3) | 0x00040001);
}
void mainboard_rcba_config(void)
diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c
index 7539dd7f51..6690c6863c 100644
--- a/src/mainboard/google/stout/romstage.c
+++ b/src/mainboard/google/stout/romstage.c
@@ -41,9 +41,6 @@ void pch_enable_lpc(void)
*/
pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
CNF1_LPC_EN | FDD_LPC_EN);
-
- /* Stout EC Decode Range Port68/6C */
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (0x68 | 0x40001));
}
void mainboard_rcba_config(void)
diff --git a/src/mainboard/hp/2570p/devicetree.cb b/src/mainboard/hp/2570p/devicetree.cb
index 585d61d134..79a84b73c2 100644
--- a/src/mainboard/hp/2570p/devicetree.cb
+++ b/src/mainboard/hp/2570p/devicetree.cb
@@ -46,6 +46,7 @@ chip northbridge/intel/sandybridge
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "docking_supported" = "0"
+ # mailbox at 0x200/0x201 and PM1 at 0x220
register "gen1_dec" = "0x007c0201"
register "gen2_dec" = "0x000c0101"
register "gen3_dec" = "0x00fcfe01"
diff --git a/src/mainboard/hp/2570p/romstage.c b/src/mainboard/hp/2570p/romstage.c
index 21e3ceaa3d..6401909dd5 100644
--- a/src/mainboard/hp/2570p/romstage.c
+++ b/src/mainboard/hp/2570p/romstage.c
@@ -28,8 +28,6 @@ void pch_enable_lpc(void)
*/
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
- /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);
}
void mainboard_rcba_config(void)
diff --git a/src/mainboard/hp/2760p/devicetree.cb b/src/mainboard/hp/2760p/devicetree.cb
index 515d20f761..a301857b7a 100644
--- a/src/mainboard/hp/2760p/devicetree.cb
+++ b/src/mainboard/hp/2760p/devicetree.cb
@@ -55,6 +55,7 @@ chip northbridge/intel/sandybridge
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "docking_supported" = "0"
+ # mailbox at 0x200/0x201 and PM1 at 0x220
register "gen1_dec" = "0x007c0201"
register "gen2_dec" = "0x000c0101"
register "gen3_dec" = "0x00fcfe01"
diff --git a/src/mainboard/hp/2760p/romstage.c b/src/mainboard/hp/2760p/romstage.c
index 68af61ba22..ba6f9566cf 100644
--- a/src/mainboard/hp/2760p/romstage.c
+++ b/src/mainboard/hp/2760p/romstage.c
@@ -27,8 +27,6 @@ void pch_enable_lpc(void)
*/
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
- /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);
}
void mainboard_rcba_config(void)
diff --git a/src/mainboard/hp/8460p/devicetree.cb b/src/mainboard/hp/8460p/devicetree.cb
index 79259b4def..a06aea9669 100644
--- a/src/mainboard/hp/8460p/devicetree.cb
+++ b/src/mainboard/hp/8460p/devicetree.cb
@@ -54,6 +54,7 @@ chip northbridge/intel/sandybridge
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "docking_supported" = "0"
+ # mailbox at 0x200/0x201 and PM1 at 0x220
register "gen1_dec" = "0x007c0201"
register "gen2_dec" = "0x000c0101"
register "gen3_dec" = "0x00fcfe01"
diff --git a/src/mainboard/hp/8460p/romstage.c b/src/mainboard/hp/8460p/romstage.c
index a3fb5f095f..f30c3a8d27 100644
--- a/src/mainboard/hp/8460p/romstage.c
+++ b/src/mainboard/hp/8460p/romstage.c
@@ -34,8 +34,6 @@ void pch_enable_lpc(void)
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
LPT_LPC_EN | COMA_LPC_EN);
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
- /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);
}
void mainboard_rcba_config(void)
diff --git a/src/mainboard/hp/8470p/devicetree.cb b/src/mainboard/hp/8470p/devicetree.cb
index 2a115cc62a..471537218e 100644
--- a/src/mainboard/hp/8470p/devicetree.cb
+++ b/src/mainboard/hp/8470p/devicetree.cb
@@ -55,6 +55,7 @@ chip northbridge/intel/sandybridge
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "docking_supported" = "0"
+ # mailbox at 0x200/0x201 and PM1 at 0x220
register "gen1_dec" = "0x007c0201"
register "gen2_dec" = "0x000c0101"
register "gen3_dec" = "0x00fcfe01"
diff --git a/src/mainboard/hp/8470p/romstage.c b/src/mainboard/hp/8470p/romstage.c
index a8761739d5..b1375e815b 100644
--- a/src/mainboard/hp/8470p/romstage.c
+++ b/src/mainboard/hp/8470p/romstage.c
@@ -33,8 +33,6 @@ void pch_enable_lpc(void)
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
LPT_LPC_EN | COMA_LPC_EN);
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
- /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);
}
void mainboard_rcba_config(void)
diff --git a/src/mainboard/hp/8770w/devicetree.cb b/src/mainboard/hp/8770w/devicetree.cb
index 7d74c940de..d98402c540 100644
--- a/src/mainboard/hp/8770w/devicetree.cb
+++ b/src/mainboard/hp/8770w/devicetree.cb
@@ -43,6 +43,7 @@ chip northbridge/intel/sandybridge
chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
register "c2_latency" = "0x0065"
register "docking_supported" = "0"
+ # mailbox at 0x200/0x201 and PM1 at 0x220
register "gen1_dec" = "0x007c0201"
register "gen2_dec" = "0x000c0101"
register "gen3_dec" = "0x00fcfe01"
diff --git a/src/mainboard/hp/8770w/romstage.c b/src/mainboard/hp/8770w/romstage.c
index a7f6b22aa3..8956b08b7b 100644
--- a/src/mainboard/hp/8770w/romstage.c
+++ b/src/mainboard/hp/8770w/romstage.c
@@ -34,8 +34,6 @@ void pch_enable_lpc(void)
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
LPT_LPC_EN | COMA_LPC_EN);
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
- /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);
}
void mainboard_rcba_config(void)
diff --git a/src/mainboard/hp/folio_9470m/devicetree.cb b/src/mainboard/hp/folio_9470m/devicetree.cb
index 5d4e5b8ea2..d626934343 100644
--- a/src/mainboard/hp/folio_9470m/devicetree.cb
+++ b/src/mainboard/hp/folio_9470m/devicetree.cb
@@ -46,6 +46,7 @@ chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "docking_supported" = "0"
+ # mailbox at 0x200/0x201 and PM1 at 0x220
register "gen1_dec" = "0x007c0201"
register "gen2_dec" = "0x000c0101"
register "gen3_dec" = "0x00fcfe01"
diff --git a/src/mainboard/hp/folio_9470m/romstage.c b/src/mainboard/hp/folio_9470m/romstage.c
index db3296c457..8ff7813cd9 100644
--- a/src/mainboard/hp/folio_9470m/romstage.c
+++ b/src/mainboard/hp/folio_9470m/romstage.c
@@ -30,8 +30,6 @@ void pch_enable_lpc(void)
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
- /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);
}
void mainboard_rcba_config(void)
diff --git a/src/mainboard/hp/revolve_810_g1/devicetree.cb b/src/mainboard/hp/revolve_810_g1/devicetree.cb
index 4d0d6395eb..ad69ca27e4 100644
--- a/src/mainboard/hp/revolve_810_g1/devicetree.cb
+++ b/src/mainboard/hp/revolve_810_g1/devicetree.cb
@@ -46,6 +46,7 @@ chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "docking_supported" = "0"
+ # mailbox at 0x200/0x201 and PM1 at 0x220
register "gen1_dec" = "0x007c0201"
register "gen2_dec" = "0x000c0101"
register "gen3_dec" = "0x00fcfe01"
diff --git a/src/mainboard/hp/revolve_810_g1/romstage.c b/src/mainboard/hp/revolve_810_g1/romstage.c
index f62024c3e6..5f8df63f5c 100644
--- a/src/mainboard/hp/revolve_810_g1/romstage.c
+++ b/src/mainboard/hp/revolve_810_g1/romstage.c
@@ -33,8 +33,6 @@ void pch_enable_lpc(void)
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
- /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);
}
void mainboard_rcba_config(void)
diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb
index 60072b0995..4ed1f3c694 100644
--- a/src/mainboard/intel/emeraldlake2/devicetree.cb
+++ b/src/mainboard/intel/emeraldlake2/devicetree.cb
@@ -44,8 +44,11 @@ chip northbridge/intel/sandybridge
register "sata_port_map" = "0x3f"
+ register "gen1_dec" = "0x00fc1601"
+ # runtime_port registers
+ register "gen2_dec" = "0x000c0181"
# SuperIO range is 0x700-0x73f
- register "gen2_dec" = "0x003c0701"
+ register "gen3_dec" = "0x003c0701"
register "c2_latency" = "1"
register "p_cnt_throttling_supported" = "0"
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index 9a9fc24677..a28ae78f28 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -39,12 +39,6 @@ void pch_enable_lpc(void)
u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN;
pci_write_config16(dev, LPC_EN, lpc_config);
- /* Map 256 bytes at 0x1600 to the LPC bus. */
- pci_write_config32(dev, LPC_GEN1_DEC, 0xfc1601);
-
- /* Map a range for the runtime_port registers to the LPC bus. */
- pci_write_config32(dev, LPC_GEN2_DEC, 0xc0181);
-
/* Enable COM1 */
if (sio1007_enable_uart_at(SIO_PORT)) {
pci_write_config16(dev, LPC_EN,
diff --git a/src/mainboard/lenovo/l520/romstage.c b/src/mainboard/lenovo/l520/romstage.c
index c8003ae0a6..426ac4e6fa 100644
--- a/src/mainboard/lenovo/l520/romstage.c
+++ b/src/mainboard/lenovo/l520/romstage.c
@@ -29,10 +29,6 @@ void pch_enable_lpc(void)
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
LPT_LPC_EN);
-
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1611);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0x040069);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0x0c0701);
}
void mainboard_rcba_config(void)
diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/romstage.c
index 32a3cc2c7d..dd8fc17268 100644
--- a/src/mainboard/lenovo/s230u/romstage.c
+++ b/src/mainboard/lenovo/s230u/romstage.c
@@ -30,9 +30,6 @@
void pch_enable_lpc(void)
{
pci_write_config16(PCH_LPC_DEV, LPC_EN, MC_LPC_EN | KBC_LPC_EN);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc0701);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0xc0069);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0xc06a1);
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
/* Memory map KB9012 EC registers */
diff --git a/src/mainboard/lenovo/t420/romstage.c b/src/mainboard/lenovo/t420/romstage.c
index 806c72a3be..ebf5aed0f1 100644
--- a/src/mainboard/lenovo/t420/romstage.c
+++ b/src/mainboard/lenovo/t420/romstage.c
@@ -56,10 +56,6 @@ void pch_enable_lpc(void)
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
-
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
diff --git a/src/mainboard/lenovo/t420s/romstage.c b/src/mainboard/lenovo/t420s/romstage.c
index 9c5171371c..49de58d8d1 100644
--- a/src/mainboard/lenovo/t420s/romstage.c
+++ b/src/mainboard/lenovo/t420s/romstage.c
@@ -56,10 +56,6 @@ void pch_enable_lpc(void)
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
-
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
diff --git a/src/mainboard/lenovo/t430/romstage.c b/src/mainboard/lenovo/t430/romstage.c
index db50bb3017..1f4b90d7f9 100644
--- a/src/mainboard/lenovo/t430/romstage.c
+++ b/src/mainboard/lenovo/t430/romstage.c
@@ -55,9 +55,6 @@ void pch_enable_lpc(void)
/* Enable TPM, EC, PS/2 Keyboard/Mouse */
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
-
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC,
- (0x0c << 16) | EC_LENOVO_PMH7_BASE | 1);
}
void mainboard_rcba_config(void)
diff --git a/src/mainboard/lenovo/t430s/romstage.c b/src/mainboard/lenovo/t430s/romstage.c
index 4edd5c6131..e590bb6c67 100644
--- a/src/mainboard/lenovo/t430s/romstage.c
+++ b/src/mainboard/lenovo/t430s/romstage.c
@@ -26,10 +26,6 @@ void pch_enable_lpc(void)
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
-
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c
index ebff37ff9c..5c23b8e06f 100644
--- a/src/mainboard/lenovo/t520/romstage.c
+++ b/src/mainboard/lenovo/t520/romstage.c
@@ -58,10 +58,6 @@ void pch_enable_lpc(void)
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
-
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c
index 24e2d9cde0..67cf97c486 100644
--- a/src/mainboard/lenovo/t530/romstage.c
+++ b/src/mainboard/lenovo/t530/romstage.c
@@ -58,10 +58,6 @@ void pch_enable_lpc(void)
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
-
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
diff --git a/src/mainboard/lenovo/x131e/romstage.c b/src/mainboard/lenovo/x131e/romstage.c
index ea550aa143..79a2276fd0 100644
--- a/src/mainboard/lenovo/x131e/romstage.c
+++ b/src/mainboard/lenovo/x131e/romstage.c
@@ -26,11 +26,6 @@ void pch_enable_lpc(void)
/* Enable TPM, EC, PS/2 Keyboard/Mouse */
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
-
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c1611);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0x00040069);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0x000c0701);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x000c06a1);
}
void mainboard_rcba_config(void)
diff --git a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c
index a951fbc72e..f666671dd6 100644
--- a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c
+++ b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c
@@ -35,10 +35,6 @@ void pch_enable_lpc(void)
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
-
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c
index 5f9a931340..9ecb8a3e1e 100644
--- a/src/mainboard/lenovo/x220/romstage.c
+++ b/src/mainboard/lenovo/x220/romstage.c
@@ -34,10 +34,6 @@ void pch_enable_lpc(void)
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
-
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c
index 3f31141583..10cddebda3 100644
--- a/src/mainboard/lenovo/x230/romstage.c
+++ b/src/mainboard/lenovo/x230/romstage.c
@@ -31,10 +31,6 @@ void pch_enable_lpc(void)
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
-
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb
index 719947310b..feae5bf1e8 100644
--- a/src/mainboard/samsung/lumpy/devicetree.cb
+++ b/src/mainboard/samsung/lumpy/devicetree.cb
@@ -61,6 +61,7 @@ chip northbridge/intel/sandybridge
# EC range is 0xa00-0xa3f
register "gen1_dec" = "0x003c0a01"
register "gen2_dec" = "0x003c0b01"
+ register "gen3_dec" = "0x00fc1601"
register "c2_latency" = "1"
register "p_cnt_throttling_supported" = "0"
diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c
index a77149d927..d4b6dd834b 100644
--- a/src/mainboard/samsung/lumpy/romstage.c
+++ b/src/mainboard/samsung/lumpy/romstage.c
@@ -43,9 +43,6 @@ void pch_enable_lpc(void)
pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN |
KBC_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);
- /* map full 256 bytes at 0x1600 to the LPC bus */
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0xfc1601);
-
try_enabling_LPC47N207_uart();
#else
/* Enable SuperIO + EC + KBC */
diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb
index 192e63d4d9..060fc40bb6 100644
--- a/src/mainboard/samsung/stumpy/devicetree.cb
+++ b/src/mainboard/samsung/stumpy/devicetree.cb
@@ -50,6 +50,7 @@ chip northbridge/intel/sandybridge
register "c2_latency" = "1"
register "p_cnt_throttling_supported" = "0"
+ register "gen1_dec" = "0x00fc1601"
# SuperIO range is 0x700-0x73f
register "gen2_dec" = "0x003c0701"
diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c
index a8e28d67ac..77fd16016d 100644
--- a/src/mainboard/samsung/stumpy/romstage.c
+++ b/src/mainboard/samsung/stumpy/romstage.c
@@ -55,9 +55,6 @@ void pch_enable_lpc(void)
pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN |\
CNF2_LPC_EN | COMA_LPC_EN);
- /* map full 256 bytes at 0x1600 to the LPC bus */
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0xfc1601);
-
try_enabling_LPC47N207_uart();
#else
/* Enable SuperIO + PS/2 Keyboard/Mouse */
diff --git a/src/mainboard/sapphire/pureplatinumh61/romstage.c b/src/mainboard/sapphire/pureplatinumh61/romstage.c
index 9a67ab295b..c7d8f0f724 100644
--- a/src/mainboard/sapphire/pureplatinumh61/romstage.c
+++ b/src/mainboard/sapphire/pureplatinumh61/romstage.c
@@ -24,10 +24,6 @@
void pch_enable_lpc(void)
{
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x2400);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0291);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c0a01);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00000000);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000);
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000);
}
diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c
index e74c3043f0..4f9cd325c6 100644
--- a/src/southbridge/intel/bd82x6x/early_pch.c
+++ b/src/southbridge/intel/bd82x6x/early_pch.c
@@ -27,6 +27,7 @@
#include <northbridge/intel/sandybridge/sandybridge.h>
#include "pch.h"
+#include "chip.h"
#define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0)
@@ -258,10 +259,31 @@ static void pch_generic_setup(void)
write_pmbase16(TCO1_CNT, 1 << 11); /* halt timer */
}
+static void pch_enable_lpc_gen_decode(void)
+{
+ const struct device *dev = pcidev_on_root(0x1f, 0);
+ const struct southbridge_intel_bd82x6x_config *config = NULL;
+
+ /* Set up generic decode ranges */
+ if (!dev)
+ return;
+ if (dev->chip_info)
+ config = dev->chip_info;
+ if (!config)
+ return;
+
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec);
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec);
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec);
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec);
+}
+
void early_pch_init(void)
{
pch_enable_lpc();
+ pch_enable_lpc_gen_decode();
+
pch_enable_bars();
pch_generic_setup();