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-rw-r--r--src/soc/intel/broadwell/Kconfig4
-rw-r--r--src/soc/intel/broadwell/pcie.c8
2 files changed, 10 insertions, 2 deletions
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index cfab4895b9..5d8d602121 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -47,6 +47,10 @@ config PCIEXP_ASPM
bool
default y
+config PCIEXP_AER
+ bool
+ default y
+
config PCIEXP_COMMON_CLOCK
bool
default y
diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c
index db948596a5..724f26328f 100644
--- a/src/soc/intel/broadwell/pcie.c
+++ b/src/soc/intel/broadwell/pcie.c
@@ -555,8 +555,12 @@ static void pch_pcie_early(struct device *dev)
pci_update_config8(dev, 0xf5, 0x0f, 0);
/* Set AER Extended Cap ID to 01h and Next Cap Pointer to 200h. */
- pci_update_config32(dev, 0x100, ~(1 << 29) & ~0xfffff,
- (1 << 29) | 0x10001);
+ if (IS_ENABLED(CONFIG_PCIEXP_AER))
+ pci_update_config32(dev, 0x100, ~(1 << 29) & ~0xfffff,
+ (1 << 29) | 0x10001);
+ else
+ pci_update_config32(dev, 0x100, ~(1 << 29) & ~0xfffff,
+ (1 << 29));
/* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */
if (IS_ENABLED(CONFIG_PCIEXP_L1_SUB_STATE))