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-rw-r--r--src/mainboard/google/hatch/romstage.c30
1 files changed, 30 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/romstage.c b/src/mainboard/google/hatch/romstage.c
index 401f41f22b..429aa09d8f 100644
--- a/src/mainboard/google/hatch/romstage.c
+++ b/src/mainboard/google/hatch/romstage.c
@@ -14,8 +14,12 @@
*/
#include <baseboard/variants.h>
+#include <console/console.h>
+#include <ec/google/chromeec/ec.h>
+#include <memory_info.h>
#include <soc/cnl_memcfg_init.h>
#include <soc/romstage.h>
+#include <string.h>
void mainboard_memory_init_params(FSPM_UPD *memupd)
{
@@ -27,3 +31,29 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
cannonlake_memcfg_init(&memupd->FspmConfig,
variant_memory_params(), &spd);
}
+
+void mainboard_get_dram_part_num(const char **part_num, size_t *len)
+{
+ static char part_num_store[DIMM_INFO_PART_NUMBER_SIZE];
+ static enum {
+ PART_NUM_NOT_READ,
+ PART_NUM_AVAILABLE,
+ PART_NUM_NOT_IN_CBI,
+ } part_num_state = PART_NUM_NOT_READ;
+
+ if (part_num_state == PART_NUM_NOT_READ) {
+ if (google_chromeec_cbi_get_dram_part_num(&part_num_store[0],
+ sizeof(part_num_store)) < 0) {
+ printk(BIOS_ERR, "No DRAM part number in CBI!\n");
+ part_num_state = PART_NUM_NOT_IN_CBI;
+ } else {
+ part_num_state = PART_NUM_AVAILABLE;
+ }
+ }
+
+ if (part_num_state == PART_NUM_NOT_IN_CBI)
+ return;
+
+ *part_num = &part_num_store[0];
+ *len = strlen(part_num_store) + 1;
+}