diff options
Diffstat (limited to 'src')
62 files changed, 151 insertions, 206 deletions
diff --git a/src/arch/arm/tables.c b/src/arch/arm/tables.c index 682c2bc39e..7f8e2a03f0 100644 --- a/src/arch/arm/tables.c +++ b/src/arch/arm/tables.c @@ -28,14 +28,14 @@ void bootmem_arch_add_ranges(void) { DECLARE_OPTIONAL_REGION(ttb_subtables); - bootmem_add_range((uintptr_t)_ttb, _ttb_size, BM_MEM_RAMSTAGE); - bootmem_add_range((uintptr_t)_ttb_subtables, _ttb_subtables_size, + bootmem_add_range((uintptr_t)_ttb, REGION_SIZE(ttb), BM_MEM_RAMSTAGE); + bootmem_add_range((uintptr_t)_ttb_subtables, REGION_SIZE(ttb_subtables), BM_MEM_RAMSTAGE); if (!IS_ENABLED(CONFIG_COMMON_CBFS_SPI_WRAPPER)) return; bootmem_add_range((uintptr_t)_postram_cbfs_cache, - _postram_cbfs_cache_size, BM_MEM_RAMSTAGE); + REGION_SIZE(postram_cbfs_cache), BM_MEM_RAMSTAGE); } void lb_arch_add_records(struct lb_header *header) diff --git a/src/arch/arm64/tables.c b/src/arch/arm64/tables.c index ec949fd83b..b0010c4b9e 100644 --- a/src/arch/arm64/tables.c +++ b/src/arch/arm64/tables.c @@ -28,15 +28,17 @@ void arch_write_tables(uintptr_t coreboot_table) void bootmem_arch_add_ranges(void) { - bootmem_add_range((uintptr_t)_ttb, _ttb_size, BM_MEM_RAMSTAGE); + bootmem_add_range((uintptr_t)_ttb, REGION_SIZE(ttb), BM_MEM_RAMSTAGE); - if (IS_ENABLED(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) && _bl31_size > 0) - bootmem_add_range((uintptr_t)_bl31, _bl31_size, BM_MEM_BL31); + if (IS_ENABLED(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) && + REGION_SIZE(bl31) > 0) + bootmem_add_range((uintptr_t)_bl31, REGION_SIZE(bl31), + BM_MEM_BL31); if (!IS_ENABLED(CONFIG_COMMON_CBFS_SPI_WRAPPER)) return; bootmem_add_range((uintptr_t)_postram_cbfs_cache, - _postram_cbfs_cache_size, BM_MEM_RAMSTAGE); + REGION_SIZE(postram_cbfs_cache), BM_MEM_RAMSTAGE); } void lb_arch_add_records(struct lb_header *header) diff --git a/src/arch/mips/cache.c b/src/arch/mips/cache.c index e17075c081..62c20f34a3 100644 --- a/src/arch/mips/cache.c +++ b/src/arch/mips/cache.c @@ -111,5 +111,6 @@ void arch_segment_loaded(uintptr_t start, size_t size, int flags) { cache_invalidate_all(start, size); if (flags & SEG_FINAL) - cache_invalidate_all((uintptr_t)_cbfs_cache, _cbfs_cache_size); + cache_invalidate_all((uintptr_t)_cbfs_cache, + REGION_SIZE(cbfs_cache)); } diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index b5a94982a6..e455b45612 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -172,7 +172,8 @@ void acpi_prepare_resume_backup(void) if (IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)) return; - backup_create_or_update(NULL, (uintptr_t)_program, _program_size); + backup_create_or_update(NULL, (uintptr_t)_program, + REGION_SIZE(program)); } #define WAKEUP_BASE 0x600 diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c index 278d50f833..062ee402f1 100644 --- a/src/cpu/x86/pae/pgtbl.c +++ b/src/cpu/x86/pae/pgtbl.c @@ -239,12 +239,12 @@ int paging_enable_for_car(const char *pdpt_name, const char *pt_name) if (!ENV_CACHE_AS_RAM) return -1; - if (read_from_cbfs(pdpt_name, _pdpt, _pdpt_size)) { + if (read_from_cbfs(pdpt_name, _pdpt, REGION_SIZE(pdpt))) { printk(BIOS_ERR, "Couldn't load pdpt\n"); return -1; } - if (read_from_cbfs(pt_name, _pagetables, _pagetables_size)) { + if (read_from_cbfs(pt_name, _pagetables, REGION_SIZE(pagetables))) { printk(BIOS_ERR, "Couldn't load page tables\n"); return -1; } diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index bb64cd5fef..1eeede586d 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -398,7 +398,7 @@ void fsp_memory_init(bool s3wake) memranges_init_empty(&memmap, &freeranges[0], ARRAY_SIZE(freeranges)); memranges_insert(&memmap, (uintptr_t)_car_region_start, _car_relocatable_data_end - _car_region_start, 0); - memranges_insert(&memmap, (uintptr_t)_program, _program_size, 0); + memranges_insert(&memmap, (uintptr_t)_program, REGION_SIZE(program), 0); if (!IS_ENABLED(CONFIG_FSP_M_XIP)) status = load_fspm_mem(&hdr, &file_data, &memmap); diff --git a/src/drivers/spi/cbfs_spi.c b/src/drivers/spi/cbfs_spi.c index 3e5f2af889..e311752dee 100644 --- a/src/drivers/spi/cbfs_spi.c +++ b/src/drivers/spi/cbfs_spi.c @@ -105,7 +105,7 @@ static void switch_to_postram_cache(int unused) boot_device_init(); if (_preram_cbfs_cache != _postram_cbfs_cache) mmap_helper_device_init(&mdev, _postram_cbfs_cache, - _postram_cbfs_cache_size); + REGION_SIZE(postram_cbfs_cache)); } ROMSTAGE_CBMEM_INIT_HOOK(switch_to_postram_cache); @@ -122,7 +122,7 @@ void boot_device_init(void) spi_flash_init_done = true; - mmap_helper_device_init(&mdev, _cbfs_cache, _cbfs_cache_size); + mmap_helper_device_init(&mdev, _cbfs_cache, REGION_SIZE(cbfs_cache)); } /* Return the CBFS boot device. */ diff --git a/src/include/symbols.h b/src/include/symbols.h index abb9fbecbc..8786db78bd 100644 --- a/src/include/symbols.h +++ b/src/include/symbols.h @@ -18,111 +18,53 @@ #include <types.h> -extern u8 _sram[]; -extern u8 _esram[]; -#define _sram_size (_esram - _sram) - extern u8 _dram[]; -extern u8 _timestamp[]; -extern u8 _etimestamp[]; -#define _timestamp_size (_etimestamp - _timestamp) - -extern u8 _preram_cbmem_console[]; -extern u8 _epreram_cbmem_console[]; -#define _preram_cbmem_console_size \ - (_epreram_cbmem_console - _preram_cbmem_console) - -extern u8 _cbmem_init_hooks[]; -extern u8 _ecbmem_init_hooks[]; -#define _cbmem_init_hooks_size (_ecbmem_init_hooks - _cbmem_init_hooks) - -extern u8 _stack[]; -extern u8 _estack[]; -#define _stack_size (_estack - _stack) - -extern u8 _pagetables[]; -extern u8 _epagetables[]; -#define _pagetables_size (_epagetables - _pagetables) +#define REGION_SIZE(name) (_e##name - _##name) -extern u8 _preram_cbfs_cache[]; -extern u8 _epreram_cbfs_cache[]; -#define _preram_cbfs_cache_size (_epreram_cbfs_cache - _preram_cbfs_cache) +#define DECLARE_REGION(name) \ + extern u8 _##name[]; \ + extern u8 _e##name[]; -extern u8 _postram_cbfs_cache[]; -extern u8 _epostram_cbfs_cache[]; -#define _postram_cbfs_cache_size (_epostram_cbfs_cache - _postram_cbfs_cache) - -extern u8 _cbfs_cache[]; -extern u8 _ecbfs_cache[]; -#define _cbfs_cache_size (_ecbfs_cache - _cbfs_cache) - -extern u8 _payload[]; -extern u8 _epayload[]; -#define _payload_size (_epayload - _payload) +DECLARE_REGION(sram) +DECLARE_REGION(timestamp) +DECLARE_REGION(preram_cbmem_console) +DECLARE_REGION(cbmem_init_hooks) +DECLARE_REGION(stack) +DECLARE_REGION(preram_cbfs_cache) +DECLARE_REGION(postram_cbfs_cache) +DECLARE_REGION(cbfs_cache) +DECLARE_REGION(payload) /* "program" always refers to the current execution unit. */ -extern u8 _program[]; -extern u8 _eprogram[]; -#define _program_size (_eprogram - _program) - +DECLARE_REGION(program) /* _<stage>_size is always the maximum amount allocated in memlayout, whereas - * _program_size gives the actual memory footprint *used* by current stage. */ -extern u8 _decompressor[]; -extern u8 _edecompressor[]; -#define _decompressor_size (_edecompressor - _decompressor) - -extern u8 _bootblock[]; -extern u8 _ebootblock[]; -#define _bootblock_size (_ebootblock - _bootblock) - -extern u8 _romstage[]; -extern u8 _eromstage[]; -#define _romstage_size (_eromstage - _romstage) - -extern u8 _ramstage[]; -extern u8 _eramstage[]; -#define _ramstage_size (_eramstage - _ramstage) - -extern u8 _verstage[]; -extern u8 _everstage[]; -#define _verstage_size (_everstage - _verstage) + _program_size gives the actual memory footprint *used* by current stage. */ +DECLARE_REGION(decompressor) +DECLARE_REGION(bootblock) +DECLARE_REGION(verstage) +DECLARE_REGION(romstage) +DECLARE_REGION(postcar) +DECLARE_REGION(ramstage) /* Arch-specific, move to <arch/symbols.h> if they become too many. */ -extern u8 _ttb[]; -extern u8 _ettb[]; -#define _ttb_size (_ettb - _ttb) - -extern u8 _ttb_subtables[]; -extern u8 _ettb_subtables[]; -#define _ttb_subtables_size (_ettb_subtables - _ttb_subtables) - -extern u8 _dma_coherent[]; -extern u8 _edma_coherent[]; -#define _dma_coherent_size (_edma_coherent - _dma_coherent) - -extern u8 _soc_registers[]; -extern u8 _esoc_registers[]; -#define _soc_registers_size (_esoc_registers - _soc_registers) +DECLARE_REGION(pagetables) +DECLARE_REGION(ttb) +DECLARE_REGION(ttb_subtables) +DECLARE_REGION(dma_coherent) +DECLARE_REGION(soc_registers) +DECLARE_REGION(framebuffer) +DECLARE_REGION(pdpt) +DECLARE_REGION(bl31) -extern u8 _framebuffer[]; -extern u8 _eframebuffer[]; -#define _framebuffer_size (_eframebuffer - _framebuffer) - -extern u8 _pdpt[]; -extern u8 _epdpt[]; -#define _pdpt_size (_epdpt - _pdpt) - -extern u8 _bl31[]; -extern u8 _ebl31[]; -#define _bl31_size (_ebl31 - _bl31) - -/* Put this into a .c file accessing a linker script region to mark that region +/* + * Put this into a .c file accessing a linker script region to mark that region * as "optional". If it is defined in memlayout.ld (or anywhere else), the * values from that definition will be used. If not, start, end and size will * all evaluate to 0. (We can't explicitly assign the symbols to 0 in the - * assembly due to https://sourceware.org/bugzilla/show_bug.cgi?id=1038.) */ + * assembly due to https://sourceware.org/bugzilla/show_bug.cgi?id=1038.) + */ #define DECLARE_OPTIONAL_REGION(name) asm (".weak _" #name ", _e" #name) #endif /* __SYMBOLS_H */ diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c index f2ada522eb..037e913e93 100644 --- a/src/lib/bootblock.c +++ b/src/lib/bootblock.c @@ -33,7 +33,8 @@ asmlinkage void bootblock_main_with_timestamp(uint64_t base_timestamp, struct timestamp_entry *timestamps, size_t num_timestamps) { /* Initialize timestamps if we have TIMESTAMP region in memlayout.ld. */ - if (IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) && _timestamp_size > 0) { + if (IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) && + REGION_SIZE(timestamp) > 0) { int i; timestamp_init(base_timestamp); for (i = 0; i < num_timestamps; i++) diff --git a/src/lib/bootmem.c b/src/lib/bootmem.c index 7cc8fff2e4..01ad3e841b 100644 --- a/src/lib/bootmem.c +++ b/src/lib/bootmem.c @@ -89,8 +89,10 @@ static void bootmem_init(void) /* Add memory used by CBMEM. */ cbmem_add_bootmem(); - bootmem_add_range((uintptr_t)_stack, _stack_size, BM_MEM_RAMSTAGE); - bootmem_add_range((uintptr_t)_program, _program_size, BM_MEM_RAMSTAGE); + bootmem_add_range((uintptr_t)_stack, REGION_SIZE(stack), + BM_MEM_RAMSTAGE); + bootmem_add_range((uintptr_t)_program, REGION_SIZE(program), + BM_MEM_RAMSTAGE); bootmem_arch_add_ranges(); bootmem_platform_add_ranges(); diff --git a/src/lib/cbmem_common.c b/src/lib/cbmem_common.c index 4010494118..d86edf013a 100644 --- a/src/lib/cbmem_common.c +++ b/src/lib/cbmem_common.c @@ -24,7 +24,7 @@ void cbmem_run_init_hooks(int is_recovery) cbmem_init_hook_t *einit_hook_ptr = (cbmem_init_hook_t *)&_ecbmem_init_hooks; - if (_cbmem_init_hooks_size == 0) + if (REGION_SIZE(cbmem_init_hooks) == 0) return; while (init_hook_ptr != einit_hook_ptr) { diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index 2f60fb5a7f..b05b747bf2 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -111,7 +111,8 @@ void cbmemc_init(void) { #ifdef __PRE_RAM__ /* Pre-RAM environments use special buffer placed by linker script. */ - init_console_ptr(_preram_cbmem_console, _preram_cbmem_console_size); + init_console_ptr(_preram_cbmem_console, + REGION_SIZE(preram_cbmem_console)); #else /* Post-RAM uses static (BSS) buffer before CBMEM is reinitialized. */ init_console_ptr(static_console, sizeof(static_console)); diff --git a/src/lib/stack.c b/src/lib/stack.c index ef45e2aee4..479ed93c05 100644 --- a/src/lib/stack.c +++ b/src/lib/stack.c @@ -30,7 +30,8 @@ it with the version available from LANL. int checkstack(void *top_of_stack, int core) { /* Not all archs use CONFIG_STACK_SIZE, those who don't set it to 0. */ - size_t stack_size = CONFIG_STACK_SIZE ? CONFIG_STACK_SIZE : _stack_size; + size_t stack_size = CONFIG_STACK_SIZE ? + CONFIG_STACK_SIZE : REGION_SIZE(stack); int i; u32 *stack = (u32 *) (top_of_stack - stack_size); diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index f84b9d5bc7..d2012d4059 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -42,7 +42,7 @@ struct __packed timestamp_cache { DECLARE_OPTIONAL_REGION(timestamp); #if defined(__PRE_RAM__) -#define USE_TIMESTAMP_REGION (_timestamp_size > 0) +#define USE_TIMESTAMP_REGION (REGION_SIZE(timestamp) > 0) #else #define USE_TIMESTAMP_REGION 0 #endif @@ -70,7 +70,7 @@ static void timestamp_cache_init(struct timestamp_cache *ts_cache, ts_cache->cache_state = TIMESTAMP_CACHE_INITIALIZED; if (USE_TIMESTAMP_REGION) - ts_cache->table.max_entries = (_timestamp_size - + ts_cache->table.max_entries = (REGION_SIZE(timestamp) - offsetof(struct timestamp_cache, entries)) / sizeof(struct timestamp_entry); } @@ -82,7 +82,7 @@ static struct timestamp_cache *timestamp_cache_get(void) if (TIMESTAMP_CACHE_IN_BSS) { ts_cache = ×tamp_cache; } else if (USE_TIMESTAMP_REGION) { - if (_timestamp_size < sizeof(*ts_cache)) + if (REGION_SIZE(timestamp) < sizeof(*ts_cache)) BUG(); ts_cache = car_get_var_ptr((void *)_timestamp); } diff --git a/src/mainboard/google/daisy/mainboard.c b/src/mainboard/google/daisy/mainboard.c index 52cb329af6..e812189923 100644 --- a/src/mainboard/google/daisy/mainboard.c +++ b/src/mainboard/google/daisy/mainboard.c @@ -326,7 +326,7 @@ static void mainboard_enable(struct device *dev) mmu_config_range(0, DRAM_START, DCACHE_OFF); mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); mmu_config_range((uintptr_t)_dma_coherent/MiB, - _dma_coherent_size/MiB, DCACHE_OFF); + REGION_SIZE(dma_coherent)/MiB, DCACHE_OFF); mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF); dcache_mmu_enable(); @@ -353,5 +353,5 @@ void lb_board(struct lb_header *header) dma->tag = LB_TAB_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; - dma->range_size = _dma_coherent_size; + dma->range_size = REGION_SIZE(dma_coherent); } diff --git a/src/mainboard/google/gale/mainboard.c b/src/mainboard/google/gale/mainboard.c index 3a69fa2ae7..9e1a0f31e2 100644 --- a/src/mainboard/google/gale/mainboard.c +++ b/src/mainboard/google/gale/mainboard.c @@ -78,7 +78,7 @@ void lb_board(struct lb_header *header) dma->tag = LB_TAB_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; - dma->range_size = _dma_coherent_size; + dma->range_size = REGION_SIZE(dma_coherent); if (IS_ENABLED(CONFIG_CHROMEOS)) { /* Retrieve the switch interface MAC addresses. */ diff --git a/src/mainboard/google/gale/mmu.c b/src/mainboard/google/gale/mmu.c index 4b0ffec301..bf46f7a0d9 100644 --- a/src/mainboard/google/gale/mmu.c +++ b/src/mainboard/google/gale/mmu.c @@ -29,7 +29,7 @@ /* DMA memory for drivers */ #define DMA_START ((uintptr_t)_dma_coherent / MiB) -#define DMA_SIZE (_dma_coherent_size / MiB) +#define DMA_SIZE (REGION_SIZE(dma_coherent) / MiB) void setup_dram_mappings(enum dram_state dram) { diff --git a/src/mainboard/google/gru/romstage.c b/src/mainboard/google/gru/romstage.c index edf440d00e..0b944febc5 100644 --- a/src/mainboard/google/gru/romstage.c +++ b/src/mainboard/google/gru/romstage.c @@ -74,5 +74,6 @@ void platform_romstage_main(void) mmu_config_range((void *)0, (uintptr_t)sdram_size_mb() * MiB, CACHED_MEM); - mmu_config_range(_dma_coherent, _dma_coherent_size, UNCACHED_MEM); + mmu_config_range(_dma_coherent, REGION_SIZE(dma_coherent), + UNCACHED_MEM); } diff --git a/src/mainboard/google/nyan/mainboard.c b/src/mainboard/google/nyan/mainboard.c index b447a4a897..47d6fb2f00 100644 --- a/src/mainboard/google/nyan/mainboard.c +++ b/src/mainboard/google/nyan/mainboard.c @@ -262,5 +262,5 @@ void lb_board(struct lb_header *header) dma->tag = LB_TAB_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; - dma->range_size = _dma_coherent_size; + dma->range_size = REGION_SIZE(dma_coherent); } diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c index b94d2dc780..2dd4c2d8bd 100644 --- a/src/mainboard/google/nyan/romstage.c +++ b/src/mainboard/google/nyan/romstage.c @@ -55,13 +55,14 @@ static void __attribute__((noinline)) romstage(void) /* Device memory below DRAM is uncached. */ mmu_config_range(0, dram_start_mb, DCACHE_OFF); /* SRAM is cached. MMU code will round size up to page size. */ - mmu_config_range((uintptr_t)_sram/MiB, DIV_ROUND_UP(_sram_size, MiB), + mmu_config_range((uintptr_t)_sram/MiB, + DIV_ROUND_UP(REGION_SIZE(sram), MiB), DCACHE_WRITEBACK); /* DRAM is cached. */ mmu_config_range(dram_start_mb, dram_size_mb, DCACHE_WRITEBACK); /* A window for DMA is uncached. */ mmu_config_range((uintptr_t)_dma_coherent/MiB, - _dma_coherent_size/MiB, DCACHE_OFF); + REGION_SIZE(dma_coherent)/MiB, DCACHE_OFF); /* The space above DRAM is uncached. */ if (dram_end_mb < 4096) mmu_config_range(dram_end_mb, 4096 - dram_end_mb, DCACHE_OFF); diff --git a/src/mainboard/google/nyan_big/mainboard.c b/src/mainboard/google/nyan_big/mainboard.c index 5457be603c..72d348da3d 100644 --- a/src/mainboard/google/nyan_big/mainboard.c +++ b/src/mainboard/google/nyan_big/mainboard.c @@ -260,5 +260,5 @@ void lb_board(struct lb_header *header) dma->tag = LB_TAB_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; - dma->range_size = _dma_coherent_size; + dma->range_size = REGION_SIZE(dma_coherent); } diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c index b94d2dc780..2dd4c2d8bd 100644 --- a/src/mainboard/google/nyan_big/romstage.c +++ b/src/mainboard/google/nyan_big/romstage.c @@ -55,13 +55,14 @@ static void __attribute__((noinline)) romstage(void) /* Device memory below DRAM is uncached. */ mmu_config_range(0, dram_start_mb, DCACHE_OFF); /* SRAM is cached. MMU code will round size up to page size. */ - mmu_config_range((uintptr_t)_sram/MiB, DIV_ROUND_UP(_sram_size, MiB), + mmu_config_range((uintptr_t)_sram/MiB, + DIV_ROUND_UP(REGION_SIZE(sram), MiB), DCACHE_WRITEBACK); /* DRAM is cached. */ mmu_config_range(dram_start_mb, dram_size_mb, DCACHE_WRITEBACK); /* A window for DMA is uncached. */ mmu_config_range((uintptr_t)_dma_coherent/MiB, - _dma_coherent_size/MiB, DCACHE_OFF); + REGION_SIZE(dma_coherent)/MiB, DCACHE_OFF); /* The space above DRAM is uncached. */ if (dram_end_mb < 4096) mmu_config_range(dram_end_mb, 4096 - dram_end_mb, DCACHE_OFF); diff --git a/src/mainboard/google/nyan_blaze/mainboard.c b/src/mainboard/google/nyan_blaze/mainboard.c index 6b448cba10..446bd533a8 100644 --- a/src/mainboard/google/nyan_blaze/mainboard.c +++ b/src/mainboard/google/nyan_blaze/mainboard.c @@ -260,5 +260,5 @@ void lb_board(struct lb_header *header) dma->tag = LB_TAB_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; - dma->range_size = _dma_coherent_size; + dma->range_size = REGION_SIZE(dma_coherent); } diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c index e44381f238..30278f9614 100644 --- a/src/mainboard/google/nyan_blaze/romstage.c +++ b/src/mainboard/google/nyan_blaze/romstage.c @@ -57,7 +57,8 @@ static void __attribute__((noinline)) romstage(void) /* Device memory below DRAM is uncached. */ mmu_config_range(0, dram_start_mb, DCACHE_OFF); /* SRAM is cached. MMU code will round size up to page size. */ - mmu_config_range((uintptr_t)_sram/MiB, DIV_ROUND_UP(_sram_size, MiB), + mmu_config_range((uintptr_t)_sram/MiB, + DIV_ROUND_UP(REGION_SIZE(sram), MiB), DCACHE_WRITEBACK); /* The space above DRAM is uncached. */ if (dram_end_mb < 4096) @@ -70,7 +71,7 @@ static void __attribute__((noinline)) romstage(void) mmu_config_range(dram_start_mb, dram_size_mb, DCACHE_WRITEBACK); /* A window for DMA is uncached. */ mmu_config_range((uintptr_t)_dma_coherent/MiB, - _dma_coherent_size/MiB, DCACHE_OFF); + REGION_SIZE(dma_coherent)/MiB, DCACHE_OFF); /* * A watchdog reset only resets part of the system so it ends up in diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c index 10f150645b..a2df5f52f3 100644 --- a/src/mainboard/google/peach_pit/mainboard.c +++ b/src/mainboard/google/peach_pit/mainboard.c @@ -462,7 +462,7 @@ static void mainboard_enable(struct device *dev) /* set up caching for the DRAM */ mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); mmu_config_range((uintptr_t)_dma_coherent/MiB, - _dma_coherent_size/MiB, DCACHE_OFF); + REGION_SIZE(dma_coherent)/MiB, DCACHE_OFF); const unsigned epll_hz = 192000000; const unsigned sample_rate = 48000; @@ -487,5 +487,5 @@ void lb_board(struct lb_header *header) dma->tag = LB_TAB_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; - dma->range_size = _dma_coherent_size; + dma->range_size = REGION_SIZE(dma_coherent); } diff --git a/src/mainboard/google/storm/mainboard.c b/src/mainboard/google/storm/mainboard.c index 05f982173b..b5dbbeadb4 100644 --- a/src/mainboard/google/storm/mainboard.c +++ b/src/mainboard/google/storm/mainboard.c @@ -122,7 +122,7 @@ void lb_board(struct lb_header *header) dma->tag = LB_TAB_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; - dma->range_size = _dma_coherent_size; + dma->range_size = REGION_SIZE(dma_coherent); #if IS_ENABLED(CONFIG_CHROMEOS) /* Retrieve the switch interface MAC addresses. */ diff --git a/src/mainboard/google/storm/mmu.c b/src/mainboard/google/storm/mmu.c index ba773c57a8..9750cc16e8 100644 --- a/src/mainboard/google/storm/mmu.c +++ b/src/mainboard/google/storm/mmu.c @@ -27,7 +27,7 @@ /* DMA memory for drivers */ #define DMA_START ((uintptr_t)_dma_coherent / MiB) -#define DMA_SIZE (_dma_coherent_size / MiB) +#define DMA_SIZE (REGION_SIZE(dma_coherent) / MiB) void setup_dram_mappings(enum dram_state dram) { diff --git a/src/mainboard/google/urara/mainboard.c b/src/mainboard/google/urara/mainboard.c index b5c1b7dc31..d7ed51e584 100644 --- a/src/mainboard/google/urara/mainboard.c +++ b/src/mainboard/google/urara/mainboard.c @@ -47,7 +47,7 @@ void lb_board(struct lb_header *header) dma->tag = LB_TAB_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; - dma->range_size = _dma_coherent_size; + dma->range_size = REGION_SIZE(dma_coherent); #if IS_ENABLED(CONFIG_CHROMEOS) /* Retrieve the switch interface MAC addresses. */ diff --git a/src/mainboard/google/veyron/mainboard.c b/src/mainboard/google/veyron/mainboard.c index e435758ccb..230c0081cc 100644 --- a/src/mainboard/google/veyron/mainboard.c +++ b/src/mainboard/google/veyron/mainboard.c @@ -126,7 +126,7 @@ void lb_board(struct lb_header *header) dma->tag = LB_TAB_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; - dma->range_size = _dma_coherent_size; + dma->range_size = REGION_SIZE(dma_coherent); } void mainboard_power_on_backlight(void) diff --git a/src/mainboard/google/veyron/romstage.c b/src/mainboard/google/veyron/romstage.c index 1d85ee3eed..9d410492b6 100644 --- a/src/mainboard/google/veyron/romstage.c +++ b/src/mainboard/google/veyron/romstage.c @@ -102,7 +102,7 @@ void main(void) mmu_config_range((uintptr_t)_dram/MiB, sdram_size_mb(), DCACHE_WRITEBACK); mmu_config_range((uintptr_t)_dma_coherent/MiB, - _dma_coherent_size/MiB, DCACHE_OFF); + REGION_SIZE(dma_coherent)/MiB, DCACHE_OFF); cbmem_initialize_empty(); diff --git a/src/mainboard/google/veyron_mickey/mainboard.c b/src/mainboard/google/veyron_mickey/mainboard.c index 74e52caf36..4b69cb17b9 100644 --- a/src/mainboard/google/veyron_mickey/mainboard.c +++ b/src/mainboard/google/veyron_mickey/mainboard.c @@ -105,7 +105,7 @@ void lb_board(struct lb_header *header) dma->tag = LB_TAB_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; - dma->range_size = _dma_coherent_size; + dma->range_size = REGION_SIZE(dma_coherent); } void mainboard_power_on_backlight(void) diff --git a/src/mainboard/google/veyron_mickey/romstage.c b/src/mainboard/google/veyron_mickey/romstage.c index 2262bae6e7..31c3596a6a 100644 --- a/src/mainboard/google/veyron_mickey/romstage.c +++ b/src/mainboard/google/veyron_mickey/romstage.c @@ -93,7 +93,7 @@ void main(void) mmu_config_range((uintptr_t)_dram/MiB, sdram_size_mb(), DCACHE_WRITEBACK); mmu_config_range((uintptr_t)_dma_coherent/MiB, - _dma_coherent_size/MiB, DCACHE_OFF); + REGION_SIZE(dma_coherent)/MiB, DCACHE_OFF); cbmem_initialize_empty(); diff --git a/src/mainboard/google/veyron_rialto/mainboard.c b/src/mainboard/google/veyron_rialto/mainboard.c index 40914ef540..e3aa9017c1 100644 --- a/src/mainboard/google/veyron_rialto/mainboard.c +++ b/src/mainboard/google/veyron_rialto/mainboard.c @@ -111,7 +111,7 @@ void lb_board(struct lb_header *header) dma->tag = LB_TAB_DMA; dma->size = sizeof(*dma); dma->range_start = (uintptr_t)_dma_coherent; - dma->range_size = _dma_coherent_size; + dma->range_size = REGION_SIZE(dma_coherent); } void mainboard_power_on_backlight(void) diff --git a/src/mainboard/google/veyron_rialto/romstage.c b/src/mainboard/google/veyron_rialto/romstage.c index f32bf3abf1..4dd7e0cc0f 100644 --- a/src/mainboard/google/veyron_rialto/romstage.c +++ b/src/mainboard/google/veyron_rialto/romstage.c @@ -103,7 +103,7 @@ void main(void) mmu_config_range((uintptr_t)_dram/MiB, sdram_size_mb(), DCACHE_WRITEBACK); mmu_config_range((uintptr_t)_dma_coherent/MiB, - _dma_coherent_size/MiB, DCACHE_OFF); + REGION_SIZE(dma_coherent)/MiB, DCACHE_OFF); cbmem_initialize_empty(); diff --git a/src/security/vboot/common.c b/src/security/vboot/common.c index 747644a062..da4e1ca09f 100644 --- a/src/security/vboot/common.c +++ b/src/security/vboot/common.c @@ -56,7 +56,7 @@ static size_t vb2_working_data_size(void) if (IS_ENABLED(CONFIG_VBOOT_STARTS_IN_ROMSTAGE)) return vb_work_buf_size; else - return _vboot2_work_size; + return REGION_SIZE(vboot2_work); } static struct selected_region *vb2_selected_region(void) diff --git a/src/security/vboot/symbols.h b/src/security/vboot/symbols.h index ddf9d950ce..e8ea580ef2 100644 --- a/src/security/vboot/symbols.h +++ b/src/security/vboot/symbols.h @@ -16,8 +16,8 @@ #ifndef __VBOOT_SYMBOLS_H__ #define __VBOOT_SYMBOLS_H__ -extern u8 _vboot2_work[]; -extern u8 _evboot2_work[]; -#define _vboot2_work_size (_evboot2_work - _vboot2_work) +#include <symbols.h> + +DECLARE_REGION(vboot2_work) #endif /* __VBOOT_SYMBOLS_H__ */ diff --git a/src/soc/cavium/cn81xx/cpu.c b/src/soc/cavium/cn81xx/cpu.c index 9504868dff..b655d8a0ed 100644 --- a/src/soc/cavium/cn81xx/cpu.c +++ b/src/soc/cavium/cn81xx/cpu.c @@ -81,7 +81,7 @@ size_t start_cpu(size_t cpu, void (*entry_64)(size_t core_id)) return 1; /* Check stack here, instead of in cpu_secondary.S */ - if ((CONFIG_STACK_SIZE * cpu) > _stack_sec_size) + if ((CONFIG_STACK_SIZE * cpu) > REGION_SIZE(stack_sec)) return 1; /* Write the address of the main entry point */ diff --git a/src/soc/cavium/cn81xx/include/soc/cpu.h b/src/soc/cavium/cn81xx/include/soc/cpu.h index 1c6a30dda9..7d3647bda0 100644 --- a/src/soc/cavium/cn81xx/include/soc/cpu.h +++ b/src/soc/cavium/cn81xx/include/soc/cpu.h @@ -18,6 +18,7 @@ #define __SOC_CAVIUM_CN81XX_CPU_H__ #include <stdint.h> +#include <symbols.h> /** * Number of the Core on which the program is currently running. @@ -70,8 +71,6 @@ void secondary_cpu_init(size_t core_id); /* Symbols in memlayout.ld */ -extern u8 _stack_sec[]; -extern u8 _estack_sec[]; -#define _stack_sec_size (_estack_sec - _stack_sec) +DECLARE_REGION(stack_sec) #endif /* __SOC_CAVIUM_CN81XX_CPU_H__ */ diff --git a/src/soc/cavium/cn81xx/mmu.c b/src/soc/cavium/cn81xx/mmu.c index d6e7ac5ee1..17b43e77ee 100644 --- a/src/soc/cavium/cn81xx/mmu.c +++ b/src/soc/cavium/cn81xx/mmu.c @@ -31,7 +31,7 @@ void soc_mmu_init(void) * Need to use secure mem attribute, as firmware is running in ARM TZ * region. */ - mmu_config_range((void *)_ttb, _ttb_size, secure_mem); + mmu_config_range((void *)_ttb, REGION_SIZE(ttb), secure_mem); mmu_config_range((void *)_dram, sdram_size_mb() * MiB, secure_mem); /* IO space has the MSB set and is divided into 4 sub-regions: * * NCB diff --git a/src/soc/cavium/common/bootblock.c b/src/soc/cavium/common/bootblock.c index 7b9d524198..a512dffa00 100644 --- a/src/soc/cavium/common/bootblock.c +++ b/src/soc/cavium/common/bootblock.c @@ -42,7 +42,7 @@ void bootblock_main(const uint64_t reg_x0, base_timestamp = timestamp_get(); /* Initialize timestamps if we have TIMESTAMP region in memlayout.ld. */ - if (IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) && _timestamp_size > 0) + if (IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) && REGION_SIZE(timestamp) > 0) timestamp_init(base_timestamp); bootblock_soc_early_init(); diff --git a/src/soc/imgtec/pistachio/bootblock.c b/src/soc/imgtec/pistachio/bootblock.c index 91c591e345..ac4a74070c 100644 --- a/src/soc/imgtec/pistachio/bootblock.c +++ b/src/soc/imgtec/pistachio/bootblock.c @@ -54,9 +54,9 @@ static void bootblock_mmu_init(void) dram_base += null_guard_size; dram_size -= null_guard_size; } - assert(!identity_map((uint32_t)_sram, _sram_size, + assert(!identity_map((uint32_t)_sram, REGION_SIZE(sram), C0_ENTRYLO_COHERENCY_WB)); assert(!identity_map(dram_base, dram_size, C0_ENTRYLO_COHERENCY_WB)); - assert(!identity_map((uint32_t)_soc_registers, _soc_registers_size, - C0_ENTRYLO_COHERENCY_UC)); + assert(!identity_map((uint32_t)_soc_registers, + REGION_SIZE(soc_registers), C0_ENTRYLO_COHERENCY_UC)); } diff --git a/src/soc/mediatek/common/include/soc/mmu_operations.h b/src/soc/mediatek/common/include/soc/mmu_operations.h index 79c3ea022b..7fa847fd1d 100644 --- a/src/soc/mediatek/common/include/soc/mmu_operations.h +++ b/src/soc/mediatek/common/include/soc/mmu_operations.h @@ -17,6 +17,7 @@ #define __SOC_MEDIATEK_COMMON_MMU_OPERATIONS_H__ #include <arch/mmu.h> +#include <symbols.h> enum { DEV_MEM = MA_DEV | MA_S | MA_RW, @@ -26,9 +27,7 @@ enum { NONSECURE_UNCACHED_MEM = MA_MEM | MA_NS | MA_RW | MA_MEM_NC, }; -extern unsigned char _sram_l2c[]; -extern unsigned char _esram_l2c[]; -#define _sram_l2c_size (_esram_l2c - _sram_l2c) +DECLARE_REGION(sram_l2c) void mtk_soc_after_dram(void); void mtk_soc_disable_l2c_sram(void); diff --git a/src/soc/mediatek/common/mmu_operations.c b/src/soc/mediatek/common/mmu_operations.c index 44670702de..7292487bed 100644 --- a/src/soc/mediatek/common/mmu_operations.c +++ b/src/soc/mediatek/common/mmu_operations.c @@ -32,13 +32,13 @@ void mtk_mmu_init(void) mmu_config_range((void *)0, (uintptr_t)4U * GiB, DEV_MEM); /* SRAM is cached */ - mmu_config_range(_sram, _sram_size, SECURE_CACHED_MEM); + mmu_config_range(_sram, REGION_SIZE(sram), SECURE_CACHED_MEM); /* L2C SRAM is cached */ - mmu_config_range(_sram_l2c, _sram_l2c_size, SECURE_CACHED_MEM); + mmu_config_range(_sram_l2c, REGION_SIZE(sram_l2c), SECURE_CACHED_MEM); /* DMA is non-cached and is reserved for TPM & da9212 I2C DMA */ - mmu_config_range(_dma_coherent, _dma_coherent_size, + mmu_config_range(_dma_coherent, REGION_SIZE(dma_coherent), SECURE_UNCACHED_MEM); mmu_enable(); @@ -56,7 +56,7 @@ void mtk_mmu_disable_l2c_sram(void) { /* Unmap L2C SRAM so it can be reclaimed by L2 cache */ /* TODO: Implement true unmapping, and also use it for the zero-page! */ - mmu_config_range(_sram_l2c, _sram_l2c_size, DEV_MEM); + mmu_config_range(_sram_l2c, REGION_SIZE(sram_l2c), DEV_MEM); /* Careful: changing cache geometry while it's active is a bad idea! */ mmu_disable(); diff --git a/src/soc/mediatek/mt8173/flash_controller.c b/src/soc/mediatek/mt8173/flash_controller.c index 0fe9bb4e57..d63b69c174 100644 --- a/src/soc/mediatek/mt8173/flash_controller.c +++ b/src/soc/mediatek/mt8173/flash_controller.c @@ -171,10 +171,10 @@ static int nor_read(const struct spi_flash *flash, u32 addr, size_t len, if (ENV_BOOTBLOCK || ENV_VERSTAGE) { dma_buf = (uintptr_t)_dma_coherent; - dma_buf_len = _dma_coherent_size; + dma_buf_len = REGION_SIZE(dma_coherent); } else { dma_buf = (uintptr_t)_dram_dma; - dma_buf_len = _dram_dma_size; + dma_buf_len = REGION_SIZE(dram_dma); } while (len - done >= SFLASH_DMA_ALIGN) { diff --git a/src/soc/mediatek/mt8173/include/soc/symbols.h b/src/soc/mediatek/mt8173/include/soc/symbols.h index 8e2d0a4fb3..85cfd789ff 100644 --- a/src/soc/mediatek/mt8173/include/soc/symbols.h +++ b/src/soc/mediatek/mt8173/include/soc/symbols.h @@ -16,8 +16,6 @@ #ifndef __SOC_MEDIATEK_MT8173_DRAM_DMA_H__ #define __SOC_MEDIATEK_MT8173_DRAM_DMA_H__ -extern unsigned char _dram_dma[]; -extern unsigned char _edram_dma[]; -#define _dram_dma_size (_edram_dma - _dram_dma) +DECLARE_REGION(dram_dma) #endif diff --git a/src/soc/mediatek/mt8173/mmu_operations.c b/src/soc/mediatek/mt8173/mmu_operations.c index 443bc6eb4d..c80226477a 100644 --- a/src/soc/mediatek/mt8173/mmu_operations.c +++ b/src/soc/mediatek/mt8173/mmu_operations.c @@ -23,7 +23,8 @@ void mtk_soc_after_dram(void) { - mmu_config_range(_dram_dma, _dram_dma_size, NONSECURE_UNCACHED_MEM); + mmu_config_range(_dram_dma, REGION_SIZE(dram_dma), + NONSECURE_UNCACHED_MEM); mtk_mmu_disable_l2c_sram(); } diff --git a/src/soc/nvidia/tegra124/verstage.c b/src/soc/nvidia/tegra124/verstage.c index d99f1a719e..2495351f6c 100644 --- a/src/soc/nvidia/tegra124/verstage.c +++ b/src/soc/nvidia/tegra124/verstage.c @@ -30,7 +30,8 @@ static void enable_cache(void) /* Whole space is uncached. */ mmu_config_range(0, 4096, DCACHE_OFF); /* SRAM is cached. MMU code will round size up to page size. */ - mmu_config_range((uintptr_t)_sram/MiB, DIV_ROUND_UP(_sram_size, MiB), + mmu_config_range((uintptr_t)_sram/MiB, + DIV_ROUND_UP(REGION_SIZE(sram), MiB), DCACHE_WRITEBACK); mmu_disable_range(0, 1); dcache_mmu_enable(); diff --git a/src/soc/nvidia/tegra210/mmu_operations.c b/src/soc/nvidia/tegra210/mmu_operations.c index de7ae2f487..9cee6b2f29 100644 --- a/src/soc/nvidia/tegra210/mmu_operations.c +++ b/src/soc/nvidia/tegra210/mmu_operations.c @@ -45,7 +45,7 @@ static void tegra210_mmu_config(void) mmu_config_range((void *)(start * MiB), (end-start) * MiB, cachedmem); /* SRAM */ - mmu_config_range(_sram, _sram_size, cachedmem); + mmu_config_range(_sram, REGION_SIZE(sram), cachedmem); /* Add TZ carveout. */ carveout_range(CARVEOUT_TZ, &tz_base_mib, &tz_size_mib); @@ -89,8 +89,8 @@ void tegra210_mmu_init(void) * */ carveout_range(CARVEOUT_TZ, &tz_base_mib, &tz_size_mib); - assert((uintptr_t)_ttb + _ttb_size == (tz_base_mib + tz_size_mib) * MiB - && _ttb_size <= tz_size_mib * MiB); + assert((uintptr_t)_ttb + REGION_SIZE(ttb) == (tz_base_mib + tz_size_mib) + * MiB && REGION_SIZE(ttb) <= tz_size_mib * MiB); mmu_enable(); } diff --git a/src/soc/qualcomm/sdm845/include/soc/symbols.h b/src/soc/qualcomm/sdm845/include/soc/symbols.h index 163b54dc51..1c14c03d01 100644 --- a/src/soc/qualcomm/sdm845/include/soc/symbols.h +++ b/src/soc/qualcomm/sdm845/include/soc/symbols.h @@ -16,18 +16,11 @@ #ifndef _SOC_QUALCOMM_SDM845_SYMBOLS_H_ #define _SOC_QUALCOMM_SDM845_SYMBOLS_H_ +#include <symbols.h> #include <types.h> -extern u8 _ssram[]; -extern u8 _essram[]; -#define _ssram_size (_essram - _ssram) - -extern u8 _bsram[]; -extern u8 _ebsram[]; -#define _bsram_size (_ebsram - _bsram) - -extern u8 _dram_reserved[]; -extern u8 _edram_reserved[]; -#define _dram_reserved_size (_edram_reserved - _dram_reserved) +DECLARE_REGION(ssram) +DECLARE_REGION(bsram) +DECLARE_REGION(dram_reserved) #endif // _SOC_QUALCOMM_SDM845_SYMBOLS_H_ diff --git a/src/soc/qualcomm/sdm845/mmu.c b/src/soc/qualcomm/sdm845/mmu.c index 52e7733fa5..ef6c058ab3 100644 --- a/src/soc/qualcomm/sdm845/mmu.c +++ b/src/soc/qualcomm/sdm845/mmu.c @@ -28,9 +28,9 @@ void sdm845_mmu_init(void) mmu_init(); mmu_config_range((void *)(4 * KiB), ((4UL * GiB) - (4 * KiB)), DEV_MEM); - mmu_config_range((void *)_ssram, _ssram_size, CACHED_RAM); - mmu_config_range((void *)_bsram, _bsram_size, CACHED_RAM); - mmu_config_range((void *)_dma_coherent, _dma_coherent_size, + mmu_config_range((void *)_ssram, REGION_SIZE(ssram), CACHED_RAM); + mmu_config_range((void *)_bsram, REGION_SIZE(bsram), CACHED_RAM); + mmu_config_range((void *)_dma_coherent, REGION_SIZE(dma_coherent), UNCACHED_RAM); mmu_enable(); diff --git a/src/soc/qualcomm/sdm845/soc.c b/src/soc/qualcomm/sdm845/soc.c index 56e2c8456a..e4eac96276 100644 --- a/src/soc/qualcomm/sdm845/soc.c +++ b/src/soc/qualcomm/sdm845/soc.c @@ -23,7 +23,7 @@ static void soc_read_resources(struct device *dev) { ram_resource(dev, 0, (uintptr_t)_dram / KiB, DRAMSIZE4GB / KiB); reserved_ram_resource(dev, 1, (uintptr_t)_dram_reserved / KiB, - _dram_reserved_size / KiB); + REGION_SIZE(dram_reserved) / KiB); } static void soc_init(struct device *dev) diff --git a/src/soc/rockchip/rk3288/bootblock.c b/src/soc/rockchip/rk3288/bootblock.c index 7308241e17..5ccfebd583 100644 --- a/src/soc/rockchip/rk3288/bootblock.c +++ b/src/soc/rockchip/rk3288/bootblock.c @@ -33,7 +33,7 @@ void bootblock_soc_init(void) /* SRAM is tightly wedged between registers, need to use subtables. Map * write-through as equivalent for non-cacheable without XN on A17. */ mmu_config_range_kb((uintptr_t)_sram/KiB, - _sram_size/KiB, DCACHE_WRITETHROUGH); + REGION_SIZE(sram)/KiB, DCACHE_WRITETHROUGH); dcache_mmu_enable(); rkclk_configure_crypto(148500*KHz); diff --git a/src/soc/rockchip/rk3288/soc.c b/src/soc/rockchip/rk3288/soc.c index c0a2ed002e..ad679e59b9 100644 --- a/src/soc/rockchip/rk3288/soc.c +++ b/src/soc/rockchip/rk3288/soc.c @@ -34,7 +34,7 @@ static void soc_init(struct device *dev) ram_resource(dev, 0, (uintptr_t)_dram/KiB, sdram_size_mb()*(MiB/KiB)); if (display_init_required()) rk_display_init(dev, (uintptr_t)_framebuffer, - _framebuffer_size); + REGION_SIZE(framebuffer)); else printk(BIOS_INFO, "Skipping display init.\n"); } diff --git a/src/soc/rockchip/rk3399/decompressor.c b/src/soc/rockchip/rk3399/decompressor.c index f4ca5d111f..a17900de50 100644 --- a/src/soc/rockchip/rk3399/decompressor.c +++ b/src/soc/rockchip/rk3399/decompressor.c @@ -30,7 +30,7 @@ void decompressor_soc_init(void) */ mmu_config_range((void *)0, (uintptr_t)4 * GiB, DEV_MEM); - mmu_config_range(_sram, _sram_size, SECURE_MEM); + mmu_config_range(_sram, REGION_SIZE(sram), SECURE_MEM); mmu_enable(); } diff --git a/src/soc/rockchip/rk3399/include/soc/symbols.h b/src/soc/rockchip/rk3399/include/soc/symbols.h index f1487d0cb6..a40a7c48d3 100644 --- a/src/soc/rockchip/rk3399/include/soc/symbols.h +++ b/src/soc/rockchip/rk3399/include/soc/symbols.h @@ -16,12 +16,9 @@ #ifndef __SOC_SYMBOLS_H__ #define __SOC_SYMBOLS_H__ -extern unsigned char _bl31_sram[]; -extern unsigned char _ebl31_sram[]; -#define _bl31_sram_size (_ebl31_sram - _bl31_sram) +#include <symbols.h> -extern unsigned char _pmu_sram[]; -extern unsigned char _epmu_sram[]; -#define _pmu_sram_size (_epmu_sram - _pmu_sram) +DECLARE_REGION(bl31_sram) +DECLARE_REGION(pmu_sram) #endif diff --git a/src/soc/rockchip/rk3399/soc.c b/src/soc/rockchip/rk3399/soc.c index 8960c9e202..6e5e1a7f96 100644 --- a/src/soc/rockchip/rk3399/soc.c +++ b/src/soc/rockchip/rk3399/soc.c @@ -30,8 +30,10 @@ void bootmem_platform_add_ranges(void) { - bootmem_add_range((uintptr_t)_pmu_sram, _pmu_sram_size, BM_MEM_BL31); - bootmem_add_range((uintptr_t)_bl31_sram, _bl31_sram_size, BM_MEM_BL31); + bootmem_add_range((uintptr_t)_pmu_sram, REGION_SIZE(pmu_sram), + BM_MEM_BL31); + bootmem_add_range((uintptr_t)_bl31_sram, REGION_SIZE(bl31_sram), + BM_MEM_BL31); } static void soc_read_resources(struct device *dev) diff --git a/src/soc/samsung/exynos5250/alternate_cbfs.c b/src/soc/samsung/exynos5250/alternate_cbfs.c index 0687d47a5d..e7ceedb15c 100644 --- a/src/soc/samsung/exynos5250/alternate_cbfs.c +++ b/src/soc/samsung/exynos5250/alternate_cbfs.c @@ -88,7 +88,7 @@ static int sdmmc_cbfs_open(void) * figuring out the true image size from in here. Since this is mainly a * developer/debug boot mode, those shortcomings should be bearable. */ - const u32 count = _cbfs_cache_size / 512; + const u32 count = REGION_SIZE(cbfs_cache) / 512; static int first_run = 1; int (*irom_load_sdmmc)(u32 start, u32 count, void *dst) = *irom_sdmmc_read_blocks_ptr; @@ -131,7 +131,7 @@ const struct region_device *boot_device_ro(void) void boot_device_init(void) { mem_region_device_ro_init(&alternate_rdev, _cbfs_cache, - _cbfs_cache_size); + REGION_SIZE(cbfs_cache)); if (*iram_secondary_base == SECONDARY_BASE_BOOT_USB) { printk(BIOS_DEBUG, "Using Exynos alternate boot mode USB A-A\n"); diff --git a/src/soc/samsung/exynos5250/spi.c b/src/soc/samsung/exynos5250/spi.c index 9406abb302..ae67407c6d 100644 --- a/src/soc/samsung/exynos5250/spi.c +++ b/src/soc/samsung/exynos5250/spi.c @@ -179,7 +179,7 @@ void exynos_init_spi_boot_device(void) { boot_slave_regs = (void *)EXYNOS5_SPI1_BASE; - mmap_helper_device_init(&mdev, _cbfs_cache, _cbfs_cache_size); + mmap_helper_device_init(&mdev, _cbfs_cache, REGION_SIZE(cbfs_cache)); } const struct region_device *exynos_spi_boot_device(void) diff --git a/src/soc/samsung/exynos5420/alternate_cbfs.c b/src/soc/samsung/exynos5420/alternate_cbfs.c index 183c3710ef..98674ba8dc 100644 --- a/src/soc/samsung/exynos5420/alternate_cbfs.c +++ b/src/soc/samsung/exynos5420/alternate_cbfs.c @@ -92,7 +92,7 @@ static int sdmmc_cbfs_open(void) * figuring out the true image size from in here. Since this is mainly a * developer/debug boot mode, those shortcomings should be bearable. */ - const u32 count = _cbfs_cache_size / 512; + const u32 count = REGION_SIZE(cbfs_cache) / 512; static int first_run = 1; int (*irom_load_sdmmc)(u32 start, u32 count, void *dst) = *irom_sdmmc_read_blocks_ptr; @@ -138,7 +138,7 @@ const struct region_device *boot_device_ro(void) void boot_device_init(void) { mem_region_device_ro_init(&alternate_rdev, _cbfs_cache, - _cbfs_cache_size); + REGION_SIZE(cbfs_cache)); if (*iram_secondary_base == SECONDARY_BASE_BOOT_USB) { printk(BIOS_DEBUG, "Using Exynos alternate boot mode USB A-A\n"); diff --git a/src/soc/samsung/exynos5420/spi.c b/src/soc/samsung/exynos5420/spi.c index 2023b10130..3ce9457e78 100644 --- a/src/soc/samsung/exynos5420/spi.c +++ b/src/soc/samsung/exynos5420/spi.c @@ -287,7 +287,7 @@ void exynos_init_spi_boot_device(void) { boot_slave = &exynos_spi_slaves[1]; - mmap_helper_device_init(&mdev, _cbfs_cache, _cbfs_cache_size); + mmap_helper_device_init(&mdev, _cbfs_cache, REGION_SIZE(cbfs_cache)); } const struct region_device *exynos_spi_boot_device(void) diff --git a/src/vendorcode/google/chromeos/symbols.h b/src/vendorcode/google/chromeos/symbols.h index d8e1ead13f..53476455c3 100644 --- a/src/vendorcode/google/chromeos/symbols.h +++ b/src/vendorcode/google/chromeos/symbols.h @@ -16,8 +16,8 @@ #ifndef __CHROMEOS_SYMBOLS_H #define __CHROMEOS_SYMBOLS_H -extern u8 _watchdog_tombstone[]; -extern u8 _ewatchdog_tombstone[]; -#define _watchdog_tombstone_size (_ewatchdog_tombstone - _watchdog_tombstone) +#include <symbols.h> + +DECLARE_REGION(watchdog_tombstone) #endif /* __CHROMEOS_SYMBOLS_H */ diff --git a/src/vendorcode/google/chromeos/watchdog.c b/src/vendorcode/google/chromeos/watchdog.c index 61619ce0f9..1b9045ced7 100644 --- a/src/vendorcode/google/chromeos/watchdog.c +++ b/src/vendorcode/google/chromeos/watchdog.c @@ -30,7 +30,7 @@ DECLARE_OPTIONAL_REGION(watchdog_tombstone); static void elog_handle_watchdog_tombstone(void *unused) { - if (!_watchdog_tombstone_size) + if (!REGION_SIZE(watchdog_tombstone)) return; if (read32(_watchdog_tombstone) == WATCHDOG_TOMBSTONE_MAGIC) @@ -44,7 +44,7 @@ BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, void mark_watchdog_tombstone(void) { - assert(_watchdog_tombstone_size); + assert(REGION_SIZE(watchdog_tombstone)); write32(_watchdog_tombstone, WATCHDOG_TOMBSTONE_MAGIC); } |