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-rw-r--r--src/soc/intel/apollolake/acpi/globalnvs.asl5
-rw-r--r--src/soc/intel/apollolake/include/soc/nvs.h7
-rw-r--r--src/soc/intel/common/block/acpi/acpi/globalnvs.asl5
-rw-r--r--src/soc/intel/common/block/include/intelblocks/cfg.h1
-rw-r--r--src/soc/intel/common/block/include/intelblocks/nvs.h7
-rw-r--r--src/soc/intel/common/block/systemagent/systemagent.c19
-rw-r--r--src/soc/intel/skylake/acpi/globalnvs.asl5
-rw-r--r--src/soc/intel/skylake/include/soc/nvs.h7
8 files changed, 15 insertions, 41 deletions
diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl
index a512a488cd..82f41b3c64 100644
--- a/src/soc/intel/apollolake/acpi/globalnvs.asl
+++ b/src/soc/intel/apollolake/acpi/globalnvs.asl
@@ -30,9 +30,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
EPCS, 8, // 0x2C - SGX Enabled status
EMNA, 64, // 0x2D - 0x34 EPC base address
ELNG, 64, // 0x35 - 0x3C EPC Length
- E4GM, 8, // 0x3D - Enable above 4GB MMIO Resource
- A4GB, 64, // 0x3E - 0x45 Base of above 4GB MMIO Resource
- A4GS, 64, // 0x46 - 0x4D Length of above 4GB MMIO Resource
+ A4GB, 64, // 0x3D - 0x44 Base of above 4GB MMIO Resource
+ A4GS, 64, // 0x45 - 0x4C Length of above 4GB MMIO Resource
/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
Offset (0x100),
diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h
index 6ed20a0277..4668e1a07f 100644
--- a/src/soc/intel/apollolake/include/soc/nvs.h
+++ b/src/soc/intel/apollolake/include/soc/nvs.h
@@ -32,10 +32,9 @@ typedef struct global_nvs_t {
uint8_t ecps; /* 0x2C - SGX Enabled status */
uint64_t emna; /* 0x2D - 0x34 EPC base address */
uint64_t elng; /* 0x35 - 0x3C EPC Length */
- uint8_t e4gm; /* 0x3D - Enable above 4GB MMIO Resource */
- uint64_t a4gb; /* 0x3E - 0x45 Base of above 4GB MMIO Resource */
- uint64_t a4gs; /* 0x46 - 0x4D Length of above 4GB MMIO Resource */
- uint8_t unused[178];
+ uint64_t a4gb; /* 0x3D - 0x44 Base of above 4GB MMIO Resource */
+ uint64_t a4gs; /* 0x45 - 0x4C Length of above 4GB MMIO Resource */
+ uint8_t unused[179];
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;
diff --git a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl
index bd248d338b..826e718da8 100644
--- a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl
+++ b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl
@@ -34,9 +34,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
U2WE, 16, // 0x2b - 0x2c USB2 Wake Enable Bitmap
U3WE, 16, // 0x2d - 0x2e USB3 Wake Enable Bitmap
UIOR, 8, // 0x2f - UART debug controller init on S3 resume
- E4GM, 8, // 0x30 - Enable above 4GB MMIO Resource
- A4GB, 64, // 0x31 - 0x38 Base of above 4GB MMIO Resource
- A4GS, 64, // 0x39 - 0x40 Length of above 4GB MMIO Resource
+ A4GB, 64, // 0x30 - 0x37 Base of above 4GB MMIO Resource
+ A4GS, 64, // 0x38 - 0x3f Length of above 4GB MMIO Resource
/* ChromeOS specific */
Offset (0x100),
diff --git a/src/soc/intel/common/block/include/intelblocks/cfg.h b/src/soc/intel/common/block/include/intelblocks/cfg.h
index 621f0586cb..be2af4aeab 100644
--- a/src/soc/intel/common/block/include/intelblocks/cfg.h
+++ b/src/soc/intel/common/block/include/intelblocks/cfg.h
@@ -24,7 +24,6 @@ struct soc_intel_common_config {
/* PCH Thermal Trip Temperature in deg C */
uint8_t pch_thermal_trip;
struct mmc_dll_params emmc_dll;
- int enable_above_4GB_mmio;
};
/* This function to retrieve soc config structure required by common code */
diff --git a/src/soc/intel/common/block/include/intelblocks/nvs.h b/src/soc/intel/common/block/include/intelblocks/nvs.h
index 003a608f76..e1040eac3c 100644
--- a/src/soc/intel/common/block/include/intelblocks/nvs.h
+++ b/src/soc/intel/common/block/include/intelblocks/nvs.h
@@ -25,10 +25,9 @@ typedef struct global_nvs_t {
u16 u2we; /* 0x2b - 0x2c USB2 Wake Enable Bitmap */
u16 u3we; /* 0x2d - 0x2e USB3 Wake Enable Bitmap */
u8 uior; /* 0x2f - UART debug controller init on S3 resume */
- u8 e4gm; /* 0x30 - Enable above 4GB MMIO Resource */
- u64 a4gb; /* 0x31 - 0x38 Base of above 4GB MMIO Resource */
- u64 a4gs; /* 0x39 - 0x40 Length of above 4GB MMIO Resource */
- u8 unused[191];
+ u64 a4gb; /* 0x30 - 0x37 Base of above 4GB MMIO Resource */
+ u64 a4gs; /* 0x38 - 0x3f Length of above 4GB MMIO Resource */
+ u8 unused[192];
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index 3da837c0af..7355817ec2 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -96,30 +96,11 @@ static void sa_read_map_entry(struct device *dev,
*result = value;
}
-/*
- * This function will get above 4GB mmio enable config specific to soc.
- *
- * Return values:
- * 0 = Above 4GB memory is not enable
- * 1 = Above 4GB memory is enable
- */
-static int get_enable_above_4GB_mmio(void)
-{
- const struct soc_intel_common_config *common_config;
- common_config = chip_get_common_soc_structure();
-
- return common_config->enable_above_4GB_mmio;
-}
-
/* Fill MMIO resource above 4GB into GNVS */
void sa_fill_gnvs(global_nvs_t *gnvs)
{
- if (!get_enable_above_4GB_mmio())
- return;
-
struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
- gnvs->e4gm = 1;
sa_read_map_entry(sa_dev, &sa_memory_map[SA_TOUUD_REG], &gnvs->a4gb);
gnvs->a4gs = ABOVE_4GB_MEM_BASE_SIZE;
printk(BIOS_DEBUG, "PCI space above 4GB MMIO is from 0x%llx to len = 0x%llx\n",
diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl
index 8eb0f8acd4..c2584db90b 100644
--- a/src/soc/intel/skylake/acpi/globalnvs.asl
+++ b/src/soc/intel/skylake/acpi/globalnvs.asl
@@ -55,9 +55,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
EPCS, 8, // 0x43 - SGX Enabled status
EMNA, 64, // 0x44 - 0x4B EPC base address
ELNG, 64, // 0x4C - 0x53 EPC Length
- E4GM, 8, // 0x54 - Enable above 4GB MMIO Resource
- A4GB, 64, // 0x55 - 0x5C Base of above 4GB MMIO Resource
- A4GS, 64, // 0x5D - 0x64 Length of above 4GB MMIO Resource
+ A4GB, 64, // 0x54 - 0x5B Base of above 4GB MMIO Resource
+ A4GS, 64, // 0x5C - 0x63 Length of above 4GB MMIO Resource
/* IGD OpRegion */
Offset (0xb4),
diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h
index b4c669b169..630ceb7a78 100644
--- a/src/soc/intel/skylake/include/soc/nvs.h
+++ b/src/soc/intel/skylake/include/soc/nvs.h
@@ -45,10 +45,9 @@ typedef struct global_nvs_t {
u8 ecps; /* 0x43 - SGX Enabled status */
u64 emna; /* 0x44 - 0x4B EPC base address */
u64 elng; /* 0x4C - 0x53 EPC Length */
- u8 e4gm; /* 0x54 - Enable above 4GB MMIO Resource */
- u64 a4gb; /* 0x55 - 0x5C Base of above 4GB MMIO Resource */
- u64 a4gs; /* 0x5D - 0x64 Length of above 4GB MMIO Resource */
- u8 rsvd[79];
+ u64 a4gb; /* 0x54 - 0x5B Base of above 4GB MMIO Resource */
+ u64 a4gs; /* 0x5C - 0x63 Length of above 4GB MMIO Resource */
+ u8 rsvd[80];
/* IGD OpRegion */
u32 aslb; /* 0xb4 - IGD OpRegion Base Address */